Search Results - "Pressel, Klaus"

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  1. 1

    Physics of failure based lifetime modelling for sintered silver die attach in power electronics: Accelerated stress testing by isothermal bending and thermal shock in comparison by Heilmann, Jens, Wunderle, Bernhard, Zschenderlein, Uwe, Wille, Catharina, Pressel, Klaus

    Published in Microelectronics and reliability (01-06-2023)
    “…The employment of sintered silver (SAG) as die attach material is one of the most promising solutions to utilize the advantages of wide bandgap semiconductors…”
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    Journal Article
  2. 2

    Chip-Package-Board Reliability of System-in-Package Using Laminate Chip Embedding Technology Based on Cu Leadframe by Fruehauf, Peter, Munding, Andreas, Pressel, Klaus, Schwarz, Patrick, Vogt, Michael

    “…We investigate the reliability of a system-in-package (SiP) technology, which uses laminate chip embedding based on a copper leadframe. For this SiP…”
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    Journal Article
  3. 3

    Embedded wafer level ball grid array (eWLB) technology for high-frequency system-in-package applications by Wojnowski, Maciej, Pressel, Klaus

    “…The embedded wafer level ball grid array (eWLB) is a novel system integration platform introduced recently. The eWLB technology is an attractive solution for…”
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    Conference Proceeding
  4. 4

    Process technology and integration of an LED driver using chip-embedding technology by Munding, Andreas, Gruber, Martin, Pressel, Klaus, Plikat, Boris, Vogt, Michael, Fruehauf, Peter

    “…System integration for LED lighting is facing the challenge of providing many additional smart functions in one housing of small form factor. A possible way to…”
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    Conference Proceeding
  5. 5

    I. Double-Sided Cooling Technology for Emobility by Klaus, Pressel, Andreas, Grassmann, Markus, Fink, Guenter, Tutsch

    “…In this paper we introduce a device concept for double-sided cooling based on a molded module. This concept allows device shrinking and tackling the needed…”
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    Conference Proceeding
  6. 6

    Reliability experiments of sintered silver based interconnections by accelerated isothermal bending tests by Heilmann, Jens, Nikitin, Ivan, Zschenderlein, Uwe, May, Daniel, Pressel, Klaus, Wunderle, Bernhard

    Published in Microelectronics and reliability (01-07-2017)
    “…Integration of more functionality and smaller chips into decreasing package volume leads to increasing heat generation. In addition, the use of new compound…”
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    Journal Article
  7. 7

    Reliability along the Value Chain - from Chip to Board/System by Pressel, Klaus, Moser, Josef

    “…Major trend in Microelectronics is the move towards higher system integration driving increasing compactness and complexity and all at acceptable cost. This…”
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    Conference Proceeding
  8. 8

    Industrial mmWave Radar Sensor in Embedded Wafer-Level BGA Packaging Technology by Beck, Christopher, Ng, Herman Jalli, Agethen, Roman, PourMousavi, Mehran, Forstner, Hans Peter, Wojnowski, Maciej, Pressel, Klaus, Weigel, Robert, Hagelauer, Amelie, Kissinger, Dietmar

    Published in IEEE sensors journal (01-09-2016)
    “…We present highly integrated 60-GHz radar transceivers for industrial sensor applications. The bistatic and monostatic transceivers are implemented in the SiGe…”
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    Journal Article
  9. 9

    High- Q Inductors Embedded in the Fan-Out Area of an eWLB by Wojnowski, M., Issakov, V., Knoblinger, G., Pressel, K., Sommer, G., Weigel, R.

    “…We investigate high-quality (high- Q ) inductors implemented in the redistribution layer (RDL) of the fan-in and fan-out area of an embedded wafer-level ball…”
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    Journal Article
  10. 10

    High-[Formula Omitted] Inductors Embedded in the Fan-Out Area of an eWLB by Wojnowski, Maciej, Issakov, Vadim, Knoblinger, Gerhard, Pressel, Klaus, Sommer, Grit, Weigel, Robert

    “…We investigate high-quality (high-[Formula Omitted]) inductors implemented in the redistribution layer (RDL) of the fan-in and fan-out area of an embedded…”
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    Journal Article
  11. 11

    Chip/Package/Board Co-Design Methodology Applied to Full-Custom Heterogeneous Integration by Brandtner, Thomas, Pressel, Klaus, Floman, Natalia, Schultz, Michael, Vogl, Michael

    “…Heterogeneous integration leads to significant increase in design complexity. We present a modular full-custom chip/package/board co-design environment based…”
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    Conference Proceeding
  12. 12

    Recent Trends in Wafer-Level Package Technology by Schmidbauer, Philipp, Wojnowski, Maciej, Pressel, Klaus, Weigel, Robert, Hagelauer, Amelie

    “…The fast growing market for system-in-package (SiP) solutions goes along with the continous evolution of important integration platforms such as the embedded…”
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    Conference Proceeding
  13. 13

    Mechanical properties of porous silver materials depending on sintering parameters by Nikitin, Ivan, Pressel, Klaus

    “…We investigated the mechanical properties of a silver sinter paste dependent on sintering and drying conditions. For these experiments we fabricated dedicated…”
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    Conference Proceeding
  14. 14

    A 5.9-to-7.8 GHz VCO in 65 nm CMOS using high-Q inductor in an embedded Wafer Level BGA package by Issakov, V., Wojnowski, M., Knoblinger, G., Fulde, M., Pressel, K., Sommer, G.

    “…We present a 5.9-to-7.8 GHz voltage-controlled oscillator (VCO) fabricated in a 65 nm CMOS technology and assembled in a chip-scale embedded Wafer Level…”
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    Conference Proceeding
  15. 15

    Chip-package-board reliability of System-in-Package using laminate chip embedding technology based on Cu leadframe by Fruehauf, Peter, Munding, Andreas, Pressel, Klaus, Vogt, Michael, Schwarz, Patrick

    “…We investigated a System-in-Package (SiP) technology using laminate chip embedding based on a copper leadframe. This SiP technology included different Si-based…”
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    Conference Proceeding
  16. 16

    Laminate Chip Embedding Technology - Impact of Material Choice and Processing for Very Thin Die Packaging by Munding, Andreas, Kessler, Angela, Scharf, Thorsten, Plikat, Boris, Pressel, Klaus

    “…Laminate chip embedding tailored to very thin dies is an attractive package technology for the integration of logic and power dies. In this paper we report on…”
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    Conference Proceeding
  17. 17

    The H2020-ECSEL Project "iRel40" (Intelligent Reliability 4.0) by Pressel, Klaus, Moser, Josef, Rzepka, Sven, Brinkfeldt, Klas, Zhao, Susan, van Driel, Willem, Giammatteo, Paolo, Bulut, Baris, Soyturk, Mujdat, Pomante, Luigi

    “…Building on many discoveries and inventions, electronics started affecting people's everyday lives in a significant fashion following the invention of the…”
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    Conference Proceeding
  18. 18

    A current-folded up-conversion mixer and VCO with center-tapped inductor in a SiGe-HBT technology for 5-GHz wireless LAN applications by Grau, G., Langmann, U., Winkler, W., Knoll, D., Osten, J., Pressel, K.

    Published in IEEE journal of solid-state circuits (01-09-2000)
    “…This paper describes a 5.8-GHz up-conversion mixer core based on a current-folded architecture and a 5-GHz differential emitter-coupled voltage-controlled…”
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    Journal Article
  19. 19

    Accelerated reliability testing and modeling of subsystems based on sintered silver thermal interface materials by Heilmann, Jens, Nikitin, Ivan, Pressel, Klaus, Wunderle, Bernhard

    “…This paper proposes a guideline for the mechanical acceleration of end-of-lifetime prognostics of metal based die attach materials. As a such, we used first an…”
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    Conference Proceeding
  20. 20

    A novel 3D packaging concept for RF powered sensor grains by Pachler, Walther, Pressel, Klaus, Grosinger, Jasmin, Beer, Gottfried, Bosch, Wolfgang, Holweg, Gerald, Zilch, Christian, Meindl, Manfred

    “…We present a novel three-dimensional (3D) embedded wafer-level ball grid array (eWLB) system in package (SiP) solution for biochips and micro labs. This 3D SiP…”
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    Conference Proceeding