Search Results - "Premachandran, C S"

Development of a Cu/Low- k Stack Die Fine Pitch Ball Grid Array (FBGA) Package for System in Package Applications by Xiaowu Zhang, Lau, J H, Premachandran, C S, Ser-Choong Chong, Leong Ching Wai, Lee, V, Chai, T C, Kripesh, V, Sekhar, V N, Pinjala, D, Che, F X

“…Consumers' demands have driven the industry toward devices and packages with low cost, high performance, and multiple functions. Stacking two or more chips…”
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Reliability challenges for 2.5D/3D integration: An overview by Premachandran, C S, Choi, Seungman, Cimino, Salvatore, Tran-Quinn, Thuy, Burrell, Lloyd, Justison, Patrick

“…Stacking of chips vertically will reduce the interconnection resistance between the chips and also enhance data communication between them. Memory chip to…”
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A Comprehensive Wafer Level Reliability Study on 65nm Silicon Interposer by Premachandran, CS, Tran-Quinn, Thuy, Burrell, Lloyd, Justison, Patrick

“…Stacking of chips vertically will reduce the interconnection resistance and as a result enhance data communication between chips. Memory chip to logic chip…”
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Monte Carlo simulation studies of sidewall roughening during reactive ion etching by PANI, S. K, TJIPTOHARSONO, F, WONG, C. C, PREMACHANDRAN, C. S, RAMAMA, P. V, IYER, M. K

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Design and Development of Fine Pitch Copper/Low-K Wafer Level Package by Rao, Vempati Srinivasa, Xiaowu Zhang, Ho Soon Wee, Rajoo, Ranjan, Premachandran, C S, Kripesh, Vaidyanathan, Seung Wook Yoon, Lau, John H

“…Copper (Cu)/low-dielectric constant (K) structures are desired choices for advanced integrated circuits (ICs) as the IC technology moving towards fine pitch,…”
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Fabrication and Testing of a Wafer-Level Vacuum Package for MEMS Device by Premachandran, C. S., Chong, Ser Choong, Liw, Saxon, Nagarajan, Ranganathan

“…A wafer-level vacuum package with getters deposited on the cap wafer is developed for an accelerometer device. An accelerometer wafer and cap wafer is bonded…”
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Development of a Disposable Bio-Microfluidic Package With Reagents Self-Contained Reservoirs and Micro-Valves for a DNA Lab-on-a-Chip (LOC) Application by Ling Xie, Premachandran, C.S., Chew, M., Ser Choong Chong

“…A disposable self-contained microfluidic package has been developed and tested for on-chip DNA extraction from human blood for practical lab-on-a-chip…”
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Chip Package Interaction(CPI) risk assessment on 28nm Back End of Line(BEOL) stack of a large I/O chip using compact 3D FEA modeling by Shah, Chirag, Mirza, Fahad, Premachandran, C. S.

“…Chip Package Interaction (CPI) is a widely recognized quality and reliability challenge for flip-chip packages due to the ultra low-K materials used within the…”
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Novel stress-free Keep Out Zone process development for via middle TSV in 20nm planar CMOS technology by Rabie, Mohamed A., Premachandran, C. S., Ranjan, Rakesh, Natarajan, Mahadevan Iyer, Sing Fui Yap, Smith, Daniel, Thangaraju, Sarasvathi, Alapati, Ramakanth, Benistant, Francis

“…For the first time, a near-Zero Keep Out Zone TSV capability is demonstrated utilizing the Middle Of Line (MoL) layer stack process development and…”
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Impact of 3D Via Middle TSV Process on 20nm Wafer Level FEOL and BEOL Reliability by Premachandran, C. S., England, Luke, Kannan, Sukeshwar, Ranjan, Rakesh, Kong Boon Yeap, Teo, Walter, Cimino, Salvatore, Tan Jing, Haojun Zhang, Smith, Daniel, Justison, Patrick, Parameshwaran, Biju, Iyer, Natarajan Mahadeva

“…The impact of after level reliability of TSV has been studied with respect to FEOL (Front End of Line) and BEOL (Back End of Line) and aspects. A TSV keep out…”
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Efficient Bidirectional protection structure for Plasma induced damage (PID) and Electrostatic discharge (ESD) for 3D IC Integration by C.S., Premachandran, Cimino, Salvatore, Prabhu, Manjunatha

“…During metal/dielectric plasma processing for the back end of the line (BEOL), degradation of the transistor gate oxide may occur due to the plasma discharge…”
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A novel die to wafer (D2W) collective bonding method for MEMS and electronics heterogeneous 3D integration by Won Kyoung Choi, Premachandran, C S, Ling Xie, Siong Chiew Ong, He, Johnny Han, Guan Jie Yap, Aibin Yu

“…A new D2W collective bonding approach is demonstrated with functional MEMS devices with smaller than 3 × 3 mm 2 and 8 inch ASIC wafers. The new package design…”
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Design, process integration and characterization of wafer level vacuum packaging for MEMS resonator by Aibin Yu, Premachandran, C S, Nagarajan, Ranganathan, Choi Won Kyoung, Lam Quynh Trang, Kumar, Rakesh, Li Shiah Lim, Han, Johnny He, Yap Guan Jie, Damaruganath, Pinjala

“…This paper discusses wafer level vacuum sealing technology with evaporated AuSn solder for a microelectromechanical systems (MEMS) resonator without getter…”
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Impact of TSV process on 14nm FEOL and BEOL reliability by Kannan, Sukeshwar, Premachandran, C. S., Smith, Daniel, Ranjan, Rakesh, Cimino, Salvatore, Kong Boon Yeap, Wu, George, Linjun Cao, Prabhu, Manjunatha, Agarwal, Rahul, Yao, Walter, England, Luke, Justison, Patrick

“…This paper presents the impact of Through Silicon Via (TSV) process on wafer level reliability with respect to front-end of line (FEOL) and back-end of line…”
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Packaging and testing of electro-magnetically actuated silicon micro mirror for Pico-projector applications by Ling Xie, Paing Myo, Ser Choong Chong, Soon Wee Ho, Wee, J, Premachandran, C S, Wang, S, Herer, Inbal, Baram, A

“…Micro mirror packaging development for pico-projector application requires integration of magnets, silicon spacer and glass cap. A multilayer stack package has…”
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Design, Fabrication, and Assembly of an Optical Biosensor Probe Package for OCT (Optical Coherence Tomography) Application by Premachandran, C.S., Khairyanto, A., Sheng, K., Singh, J., Teo, J., Yingshun, X., Nanguang, C., Sheppard, C., Olivo, M.

“…A miniaturized optical bioprobe package is developed using a 3-D micromirror and is tested for bio-imaging application. A silicon optical bench is designed and…”
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A low stress bond pad design for low temperature solder interconnections on through silicon vias (TSVs) by Xiaowu Zhang, Rajoo, R, Selvanayagam, C S, Premachandran, C S, Choi, W K, Ho, S W, Ong, S W, Ling Xie, Pinjala, D, Sekhar, V N, Kwong, D.-L

“…Low temperature bonds are thin intermetallic bonds that are formed between devices when plated layers of different metals on each side of the component come…”
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Influence of optical probe packaging on a 3D MEMS scanning micro-mirror for optical coherence tomography (OCT) applications by Premachandran, C.S., Khairyanto, A., Chen, K., Singh, J., Sandy Xl Wang, Xu Yingshun, Chen Nanguang, Sheppard, C.J.R., Olivo, M., Lau, J.

“…An optical probe is developed for imaging in an optical coherence tomography (OCT) system. A 3D micro mirror is used for steering the beam from the source to…”
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Characterization of AuSn Solder in Laser Die Attachment for Photonic Packaging Applications by Liu Ying Ying, Premachandran, C.S., Seung Wook Yoon, Liao Ebin, Nagarajan, R., Ramana, P.V.

“…80 wt.% Au, 20 wt.% Sn solder is used in optoelectronics because it allows soldering in fluxless processes. Au-Sn solder is also applied in the field of RF and…”
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Vacuum packaging development and testing for an uncooled IR bolometer device by Premachandran, C.S., Chong, S.C., Chai, T.C., Iyer, M.

“…A vacuum package has been developed for 128/spl times/128 array IR bolometer device with Ge window having anti reflection (AR) coating. For a good vacuum…”
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