Search Results - "Posseme, N."

Alternative process for thin layer etching: Application to nitride spacer etching stopping on silicon germanium by Posseme, N., Pollet, O., Barnola, S.

“…Silicon nitride spacer etching realization is considered today as one of the most challenging of the etch process for the new devices realization. For this…”
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Topographically selective deposition by Chaker, A., Vallee, C., Pesce, V., Belahcen, S., Vallat, R., Gassilloud, R., Posseme, N., Bonvalot, M., Bsiesy, A.

“…In this paper, we present a topographically Selective Deposition process which allows the vertical only coating of three-dimensional (3D) nano-structures. This…”
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Thin layer etching of silicon nitride: A comprehensive study of selective removal using NH3/NF3 remote plasma by Posseme, N., Ah-Leung, V., Pollet, O., Arvet, C., Garcia-Barros, M.

“…Silicon nitride spacer etching realization is considered today as one of the most challenging processes for the fully depleted silicon on insulator devices…”
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First demonstration of a CMOS over CMOS 3D VLSI CoolCube™ integration on 300mm wafers by Brunet, L., Batude, P., Fenouillet-Beranger, C., Besombes, P., Hortemel, L., Ponthenier, F., Previtali, B., Tabone, C., Royer, A., Agraffeil, C., Euvrard-Colnat, C., Seignard, A., Morales, C., Fournel, F., Benaissa, L., Signamarcheix, T., Besson, P., Jourdan, M., Kachtouli, R., Benevent, V., Hartmann, J.-M, Comboroure, C., Allouti, N., Posseme, N., Vizioz, C., Arvet, C., Barnola, S., Kerdiles, S., Baud, L., Pasini, L., Lu, C.-M V., Deprat, F., Toffoli, A., Romano, G., Guedj, C., Delaye, V., Boeuf, F., Faynot, O., Vinet, M.

“…For the first time, a full 3D CMOS over CMOS CoolCube™ integration is demonstrated with a top level compatible with state of the art high performance FDSOI…”
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Patterning of narrow porous SiOCH trenches using a TiN hard mask by Darnon, M., Chevolleau, T., Eon, D., Bouyssou, R., Pelissier, B., Vallier, L., Joubert, O., Posseme, N., David, T., Bailly, F., Torres, J.

“…For the next technological generations of integrated circuits, the traditional challenges faced by etch plasmas (profile control, selectivity, critical…”
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Impact of patterning and ashing on electrical properties and reliability of interconnects in a porous SiOCH ultra low- k dielectric material by Aimadeddine, M., Arnal, V., Farcy, A., Guedj, C., Chevolleau, T., Possémé, N., David, T., Assous, M., Louveau, O., Volpi, F., Torres, J.

“…In this study, a PECVD porous SiOCH dielectric with k = 2.4 is integrated in a Cu single damascene architecture. The main issue investigated is the low k…”
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Efficiency of reducing and oxidizing ash plasmas in preventing metallic barrier diffusion into porous SiOCH by Posseme, N., Chevolleau, T., David, T., Darnon, M., Barnes, J.P., Louveau, O., Licitra, C., Jalabert, D., Feldis, H., Fayolle, M., Joubert, O.

“…This work focuses on the efficiency of reducing and oxidizing plasma chemistries in preventing metallic barrier diffusion into porous dielectric materials…”
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Process stability of SiO2 atomic layer etching in C4F6/Ar chemistry by Ronco, Antoine, Boulard, F., Pelissier, B., Posseme, N.

“…Great interest is shown toward atomic layer etching (ALE) processes due to the better control of the etching process and higher selectivity that they can…”
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In situ Post Etch Treatment on Ge-rich GST after etching in HBr-based plasma by Boixaderas, C., Canvel, Y., Fontaine, B., Lagrasta, S., Dubois, J., Gouraud, P., Posseme, N., Martinez, E.

“…After patterning of Phase Change Memory (PCM) stack, residues are growing after etching and air exposure. This kind of defect might lead to severe impacts on…”
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Prediction of porous dielectric line wiggling phenomenon with metallic hard mask: From simulation to experiment by Ducoté, J., Possémé, N., David, T., Darnon, M., Chevolleau, T., Guillermet, M.

“…The patterning of narrow trenches in porous SiOCH with a metallic hard mask can lead to the undulation of the dielectric lines between the trenches, also…”
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Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain by Barraud, S., Lapras, V., Samson, M. P., Gaben, L., Grenouillet, L., Maffini-Alvaro, V., Morand, Y., Daranlot, J., Rambal, N., Previtalli, B., Reboh, S., Tabone, C., Coquand, R., Augendre, E., Rozeau, O., Hartmann, J. M., Vizioz, C., Arvet, C., Pimenta-Barros, P., Posseme, N., Loup, V., Comboroure, C., Euvrard, C., Balan, V., Tinti, I., Audoit, G., Bernier, N., Cooper, D., Saghi, Z., Allain, F., Toffoli, A., Faynot, O., Vinet, M.

“…We report on vertically stacked horizontal Si NanoWires (NW) /p-MOSFETs fabricated with a replacement metal gate (RMG) process. For the first time, stacked-NWs…”
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Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond by Faynot, O, Andrieu, F, Weber, O, Fenouillet-Béranger, C, Perreau, P, Mazurier, J, Benoist, T, Rozeau, O, Poiroux, T, Vinet, M, Grenouillet, L, Noel, J.-P, Posseme, N, Barnola, S, Martin, F, Lapeyre, C, Cassé, M, Garros, X, Jaud, M.-A, Thomas, O, Cibrario, G, Tosti, L, Brevard, L, Tabone, C, Gaud, P, Barraud, S, Ernst, T, Deleonibus, S

“…Recent device developments and achievements have demonstrated that planar undoped channel Fully depleted SOI devices are becoming a serious alternative to Bulk…”
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Bevel contamination management in 3D integration by localized SiO2 deposition by Boulard, F., Gros, V., Porzier, C., Brunet, L., Lapras, V., Fournel, F., Truffier-Boutry, D., Autillo, D., Ruault, P., Keovisai, M., Posseme, N.

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Plasma etch challenges at 14nm and beyond technology nodes in the BEOL by Brun, Ph, Bailly, F., Guillermet, M., Aparico, E., Posseme, N.

“…With the constant scaling down in dimension, the metal hard mask strategy, integration of choice for porous SiOCH film integration, presents new issues that…”
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Etching and stripping process developments for sub-10nm FDSOI device architectures using alternative lithography techniques by Pollet, O., Barnola, S., Posseme, N., Pimenta-Barros, P.

“…To meet CD specifications required for 10nm and beyond Fully-depleted SOI devices (FDSOI) techniques alternative to EUV lithography are being developed. This…”
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Etching of porous SiOCH materials in fluorocarbon-based plasmas by Posseme, N., Chevolleau, T., Joubert, O., Vallier, L., Rochat, N.

“…This work focuses on the etching of different porous methylsilsesquioxane materials (spin on SiOCH, k = 2.2 ) with different porosity (30%, 40% and 50%) in…”
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Enabling the use of ion implantation for ultra-thin FDSOI n-MOSFETs by Vinet, M., Kumar, A., Grenouillet, L., Ponoth, S., Posseme, N., Destefanis, V., Mehta, S., Loubet, N., Le Tiec, Y., Monsieur, F., Liu, Q., Daval, N., Doris, B., Faynot, O., Poiroux, T.

“…For the first time, we extensively review to which extent ion implantation is viable for the design of n-FET transistors with gate length down to 20nm in a…”
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Implant approaches and challenges for 20nm node and beyond ETSOI devices by Ponoth, S., Vinet, M., Grenouillet, L., Kumar, A., Kulkarni, P., Liu, Q., Cheng, K., Haran, B., Posseme, N., Khakifirooz, A., Loubet, N., Mehta, S., Kuss, J., Destefanis, V., Berliner, N., Sreenivasan, R., Le Tiec, Y., Kanakasabapathy, S., Schmitz, S., Levin, T., Luning, S., Hook, T., Khare, M., Shahidi, G., Doris, B.

“…Two implantation based schemes were explored for ETSOI NFET devices targeted for the 20 nm node. Amorphization of the thin SOI is a key issue for the implant…”
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Etching process scalability and challenges for ULK materials by Chevolleau, T, Posseme, N, David, T, Bouyssou, R, Ducote, J, Bailly, F, Darnon, M, El Kodadi, M, Besacier, M, Licitra, C, Guillermet, M, Ostrovsky, A, Verove, C, Joubert, O

“…With the scaling down of integrated circuit devices, a constant effort is needed to improve the patterning technologies of interconnect stacks using either the…”
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Impact of back bias on ultra-thin body and BOX (UTBB) devices by Liu, Q., Monsieur, F., Kumar, A., Yamamoto, T., Yagishita, A., Kulkarni, P., Ponoth, S., Loubet, N., Cheng, K., Khakifirooz, A., Haran, B., Vinet, M., Cai, J., Kuss, J., Linder, B., Grenouillet, L., Mehta, S., Khare, P., Berliner, N., Levin, T., Kanakasabapathy, S., Upham, A., Sreenivasan, R., Le Tiec, Y., Posseme, N., Li, J., Demarest, J., Smalley, M., Leobandung, E., Monfray, S., Boeuf, F., Skotnicki, T., Ishimaru, K., Takayanagi, M., Kleemeier, W., Bu, H., Luning, S., Hook, T., Khare, M., Shahidi, G., Doris, B., Sampson, R.

“…We present a detailed study of back bias (V bb ) impact on UTBB devices with a gate length (L G ) of 25nm and BOX thicknesses (TBOX) of 25nm and 10nm,…”
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