Search Results - "Poon, Chi Fung"

A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET by Poon, Chi Fung, Zhang, Wenfeng, Cho, Junho, Ma, Shaojun, Wang, Yipeng, Cao, Ying, Laraba, Asma, Ho, Eugene, Lin, Winson, Wu, Daniel Zhaoyin, Tan, Kee Hian, Upadhyaya, Parag, Frans, Yohan

“…This article describes the design of a 1.24-pJ/b 112-Gb/s PAM4 transceiver test chip in 7-nm FinFET for in-package die-to-die communication. The receiver…”
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A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET by Upadhyaya, Parag, Poon, Chi Fung, Lim, Siok Wei, Cho, Junho, Roldan, Arianne, Zhang, Wenfeng, Namkoong, Jin, Pham, Toan, Xu, Bruce, Lin, Winson, Zhang, Hongtao, Narang, Nakul, Tan, Kee Hian, Zhang, Geoff, Frans, Yohan, Chang, Ken

“…The design of a dual-mode, 19-58-Gb/s four-level pulse-amplitude modulation (PAM-4) and 9.5-29-Gb/s nonreturn to zero (NRZ), transceiver in 16-nm FinFET is…”
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A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET by Upadhyaya, Parag, Chi Fung Poon, Siok Wei Lim, Junho Cho, Roldan, Arianne, Wenfeng Zhang, Jin Namkoong, Toan Pham, Xu, Bruce, Lin, Winson, Hongtao Zhang, Narang, Nakul, Kee Hian Tan, Zhang, Geoff, Frans, Yohan, Chang, Ken

“…Trends in IoT and cloud computing continue to accelerate bandwidth demand, requiring technology innovation to cover 50G, 100G and 400G ports without…”
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A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET by Hudner, James, Carey, Declan, Casey, Ronan, Hearne, Kay, de Abreu Farias Neto, Pedro Wilson, Chlis, Ilias, Erett, Marc, Chi Fung Poon, Laraba, Asma, Hongtao Zhang, Chaitanya Ambatipudi, Sai Lalith, Mahashin, David, Upadhyaya, Parag, Frans, Yohan, Chang, Ken

“…A 112Gb/s PAM4 wireline receiver testchip is implemented in 16nm FinFET. The receiver consists of continuous-time linear equalizers, a peaking capacitance…”
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A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS by Savoj, J., Hsieh, K., Upadhyaya, P., Fu-Tai An, Bekele, A., Chen, S., Xuewen Jiang, Kang Wei Lai, Chi Fung Poon, Sewani, A., Turker, D., Venna, K., Wu, D., Xu, B., Alon, E., Ken Chang

“…This paper describes the design of a fully-adaptive backplane transceiver embedded in a state-of-the-art, low-leakage, 28nm CMOS FPGA. The receive AFE utilizes…”
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A 1.24pJ/b 112Gb/s (870Gbps/mm) Transceiver for In-package Links in 7nm FinFET by Poon, Chi Fung, Zhang, Wenfeng, Cho, Junho, Ma, Shaojun, Wang, Yipeng, Cao, Ying, Laraba, Asma, Ho, Eugene, Lin, Winson, Wu, Daniel, Tan, Kee Hian, Upadhyaya, Parag, Frans, Yohan

“…This paper describes the design of a 1.24pJ/b 112Gb/s PAM4 transceiver testchip in 7nm FinFET for in-package die-to-die communication. The receiver supports…”
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