Search Results - "Pombortsis, A.S."
-
1
Formally assessing an instructional tool: a controlled experiment in software engineering
Published in IEEE transactions on education (01-02-2005)“…This work describes a controlled experiment concerning the use of a learning aid during the instructional procedure. The core issue of investigation is whether…”
Get full text
Journal Article -
2
Teaching performance evaluation of multiprocessor architectures with Mathcad and MathConnex
Published in IEEE transactions on education (01-08-2002)“…This paper presents the development of an interactive environment that facilitates the performance evaluation of multiprocessor architectures with Mathcad and…”
Get full text
Journal Article -
3
Grid-based switch fabrics: a new approach in designing fault-tolerant ATM switches
Published in Computer communications (01-10-2001)“…ATM is the switching and multiplexing technology chosen to be used in the implementation of B-ISDN, because of its superiority in fast packet switching…”
Get full text
Journal Article -
4
Analytical simulation of multiprocessor architectures under non-uniform traffic loads
Published in Mathematics and computers in simulation (15-08-2000)“…The performance analysis of network architecture is a very crucial factor in designing multiprocessor systems. Very often, simulation is the only feasible…”
Get full text
Journal Article -
5
Performability analysis of clos multiprocessor systems
Published in Information sciences (1996)“…In this paper, we consider the problem of performability of a class of multistage interconnection networks, namely, the Clos network. Performability in the…”
Get full text
Journal Article -
6
Performance analysis of multiprocessor architectures via analytical simulation
Published in 33rd Annual Simulation Symposium (SS 2000), Washington, DC, USA, 04/16-04/20/00 (2000)“…The performance analysis of network architectures is a very crucial factor in designing multiprocessor systems. Very often, simulation is the only feasible…”
Get full text
Conference Proceeding Journal Article
-
7
The fat Clos ATM switch
Published in ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357) (1999)“…This paper studies a new ATM architecture based on the implementation of channel grouping technique in the widely used Clos switch architecture. Channel…”
Get full text
Conference Proceeding -
8
Performance related analysis of L-level hierarchical shared-memory multiprocessors
Published in Proceedings of 8th Mediterranean Electrotechnical Conference on Industrial Applications in Power Systems, Computer Science and Telecommunications (MELECON 96) (1996)“…An L-level hierarchical shared memory multiprocessor architecture is considered. The base clusters consist of processors and memory modules. The other clusters…”
Get full text
Conference Proceeding -
9
On the bandwidth availability of multistage interconnection networks
Published in 1993 Euromicro Workshop on Parallel and Distributed Processing (1993)“…In this paper, we develop a model that describes the behaviour of a multistage interconnection network (MIN) interconnecting processors and memory modules,…”
Get full text
Conference Proceeding -
10
Performance analysis of Clos interconnection networks under non-uniform traffic patterns
Published in Microprocessors and microsystems (01-09-1996)“…In this paper we consider the performance behaviour of a multiprocessor system that employs Clos interconnection network under non-uniform traffic patterns…”
Get full text
Journal Article -
11
Cell availability of multiple path ATM switch
Published in MELECON '98. 9th Mediterranean Electrotechnical Conference. Proceedings (Cat. No.98CH36056) (1998)“…The switching configuration employed in an ATM network should be designed considering both performance and reliability issues. This paper presents the effects…”
Get full text
Conference Proceeding