Search Results - "Pitchumani, V."

Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization by Zhuoyuan Li, Hong, X., Qiang Zhou, Cai, Y., Bian, J., Yang, H.H., Pitchumani, V., Chung-Kuan Cheng

“…Three-dimensional (3-D) IC physical design problems are usually of higher complexity, with a greatly enlarged solution space due to multiple device structure…”
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Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning by Zhuoyuan Li, Hong, X., Qiang Zhou, Shan Zeng, Bian, J., Wenjian Yu, Yang, H.H., Pitchumani, V., Chung-Kuan Cheng

“…In this paper, we investigate thermal via (T-via) planning during three-dimensional (3-D) floorplanning. First, we consider the temperature constrained T-via…”
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Variation-aware analysis: savior of the nanometer era? by Nassif, S. R., Pitchumani, V., Rodriguez, N., Sylvester, D., Bittlestone, C., Radojcic, R.

“…VLSI engineers have traditionally used a variety of CAD analysis tools (e.g. SPICE) to deal with variability.As we go into deep sub micron issues, the analysis…”
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Multi-schedule design space exploration: an alternative synthesis framework by Dalkilic, M.E., Pitchumani, V.

“…A multi-schedule data-path synthesis framework is described that is an improvement over conventional single-schedule methods. The multi-schedule approach…”
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Taming the DFM beast into an adorable pet - a comprehensive approach by Pitchumani, V.

“…Summary form only given. Design for manufacturability, or DFM, strikes mortal fear in the heart of design and manufacturing communities. Relentless technology…”
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A Mixed HVH-VHV Algorithm for Three-Layer Channel Routing by Pitchumani, V., Qisui Zhang

“…We present a hybrid three-layer channel-routing algorithm that combines horizontal-vertical-horizontal (HVH) and vertical-horizontal-vertical (VHV) approaches…”
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Functional test generation based on unate function theory by Pitchumani, V., Soman, S.S.

“…The generation of a universal test set (UTS) for unate functions is used as a starting point. This test set is complete and minimal for the set of all…”
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A massively parallel algorithm for fault simulation on the connection machine by Narayanan, V., Pitchumani, V.

“…A massively parallel algorithm for fault simulation on the Connection Machine is presented. This algorithm achieves two to three orders of magnitude speedup…”
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Compaction of a routed channel on the connection machine by Ganguly, S., Pitchumani, V.

“…A parallel algorithm for symbolic compaction of two layered channels has been developed and implemented on the Connection Machine. It allows fast channel…”
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Restricted symbolic evaluation is fast and useful by Carter, J.L., Rosen, B.K., Smith, G.L., Pitchumani, V.

“…A method is presented for simulation with two zillion and three values. The values that are propagated by the simulation include the familiar 0, 1, and X and…”
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A VHDL fault diagnosis tool using functional fault models by Pitchumani, V., Mayor, P., Radia, N.

“…The development and implementation of an algorithm that forms the basis of a very-high-speed integrated circuit hardware description language (VHDL) fault…”
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Design for manufacturability by Pitchumani, V.

“…Summary form only given. DFM (design for manufacturability) has recently become a buzzword; it excites passion in semiconductor process, design, EDA and…”
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A Hitchhiker's Guide to the DFM Universe by Pitchumani, V.

“…This paper defines the scope of design for manufacturability (DFM) and describes a multi-layered approach to avoid, minimize and model its effects. It argues…”
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Design tools for 3D mixed mode placement by Zhuoyuan Li, Haixia Yan, Xianlong Hong, Qiang Zhou, Jinian Bian, Yang, H.H., Pitchumani, V.

“…We present a set of design tools for three dimensional (3D) mixed mode placement (MMP). The hierarchical 3D MMP design tool is composed of a hierarchical…”
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A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation by Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Yang, H., Saxena, P., Pitchumani, V.

“…An efficient and effective divide-and conquer 2.5D floorplanning algorithm is proposed for wirelength optimization. Modules are pre-partitioned into different…”
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Variation-aware analysis: savior of the nanometer era? by Joyner, W.H., Rawat, S., Nassif, S.R., Pitchumani, V., Rodriguez, N., Sylvester, D., Bittlestone, C., Radojcic, R.

“…VLSI engineers have traditionally used a variety of CAD analysis tools (e.g. SPICE) to deal with variability. As we go into deep sub micron issues, the…”
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Multi-schedule design space exploration : an alternative synthesis framework by DALKILIC, M. E, PITCHUMANI, V

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Optimal operation scheduling using resource lower bound estimations by Dalkilic, M.E., Pitchumani, V.

“…Presents an accurate resource lower bound estimation technique which leads to an efficient, and optimal solution of time-constrained as well as hardware…”
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Distributed data-path synthesis on a network of workstations by Dalkilic, M.E., Pitchumani, V.

“…Presents a distributed data-path synthesis approach which taps into the vast and cheap computing power of the distributed computing environments. The synthesis…”
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HSIM1 and HSIM2: object oriented algorithms for VHDL simulation by Ganguly, N., Pitchumani, V.

“…In this paper we present two algorithms, HSIM1 and HSIM2, for the simulation of VHDL circuit descriptions. HSIM1 and HSIM2 are both object-oriented…”
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