Search Results - "Pissors, V."

Highly Reliable Flash Memory with Self-Aligned Split-Gate Cell Embedded into High Performance 65nm CMOS for Automotive & Smartcard Applications by Shum, D., Power, J. R., Ullmann, R., Suryaputra, E., Ho, K., Hsiao, J., Tan, C. H., Langheinrich, W., Bukethal, C., Pissors, V., Tempel, G., Rohrich, M., Gratz, A., Iserhagen, A., Andersen, E. O., Paprotta, S., Dickenscheid, W., Strenz, R., Duschl, R., Kern, T., Hsieh, C. T., Huang, C. M., Ho, C. W., Kuo, H. H., Hung, C. W., Lin, Y. T., Tran, L. C.

“…A split-gate (SG) flash memory cell has been embedded in a 65nm ground-rule high performance (HP) CMOS logic process with copper low K interconnects. A gate…”
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Future trends in charge trapping memories by Kuesters, K.-H., Ludwig, C., Mikolajick, T., Nagel, N., Specht, M., Pissors, V., Schulze, N., Stein, E., Willer, J.

“…Charge trapping memories offer advantages for scaling data flash memories in the sub 50nm groundrule. This paper reviews the progress of the main concepts in…”
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A New Twin Flash™ Cell for 2 and 4 Bit Operation at 63nm Feature Size by Nagel, N., Boubekeur, H., Heinrichsdorff, F., Bach, L., Polei, V., Gupta, J., Pritchard, D., Riedel, S., Strassburg, M., Deppe, J., Bewersdorff-Sarlette, U., Muller, T., Verhoeven, M., Lattard, L., Markert, M., Ruttkowski, E., Mikalo, R., Willer, J., Schulze, N., Ludwig, C., v. Kamienski, E.G. Stein, Mikolajick, T., Isler, M., Kusters, K.-H., Shappir, A., Shur, Y., Lusky, E., Eitan, B., Pissors, V., Sachse, J.-U., Manger, D., Caspary, D., Parascandola, S., Olligs, D.

“…A 63nm Twin Flash memory cell with a size of 0.0225μm 2 / 2 (4) bits is presented. The cell is proposed for data Flash products with 4 to 16 Gbit densities. To…”
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