Search Results - "Pirsch, P."

VLSI architectures for video compression-a survey by Pirsch, P., Demassieux, N., Gehrke, W.

“…The paper presents an overview on architectures for VLSI implementations of video compression schemes as specified by standardization committees of the ITU and…”
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EVALUATION OF PENALTY FUNCTIONS FOR SEMI-GLOBAL MATCHING COST AGGREGATION by Banz, C., Pirsch, P., Blume, H.

“…The stereo matching method semi-global matching (SGM) relies on consistency constraints during the cost aggregation which are enforced by so-called penalty…”
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Hardware-Abbildung eines videobasierten Verfahrens zur echtzeitfähigen Auswertung von Winkelhistogrammen auf eine modulare Coprozessor-Architektur by Flatt, H., Tarnowsky, A., Blume, H., Pirsch, P.

“…Dieser Beitrag behandelt die Abbildung eines videobasierten Verfahrens zur echtzeitfähigen Auswertung von Winkelhistogrammen auf eine modulare…”
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Multicore system-on-chip architecture for MPEG-4 streaming video by Berekovic, M., Stolberg, H.-J., Pirsch, P.

“…The newly defined MPEG-4 Advanced Simple (AS) profile delivers single-layered streaming video in digital television (DTV) quality in the promising 1-2 Mbit/s…”
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VLSI implementations of image and video multimedia processing systems by Pirsch, P., Stolberg, H.-J.

“…An overview of very large scale integrated (VLSI) implementations of multimedia processing systems is given with particular emphasis on architectures for image…”
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Hardware-Abbildung eines videobasierten Verfahrens zur echtzeitfähigen Auswertung von Winkelhistogrammen auf eine modulare Coprozessor-Architektur by H. Flatt, A. Tarnowsky, H. Blume, P. Pirsch

“…Dieser Beitrag behandelt die Abbildung eines videobasierten Verfahrens zur echtzeitfähigen Auswertung von Winkelhistogrammen auf eine modulare…”
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Advances in picture coding by Musmann, H.G., Pirsch, P., Grallert, H.-J.

“…This paper presents a review of the advances in digital coding of video signals during the last four years. Displacement estimation algorithms for coding…”
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A 1.3-GOPS parallel DSP for high-performance image-processing applications by Hinrichs, W., Wittenburg, J.P., Lieske, H., Kloos, H., Ohmacht, M., Pirsch, P.

“…A programmable digital signal processor (DSP) for real-time image processing is presented that combines the concepts of single-instruction multiple-data (SIMD)…”
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An SoC with two multimedia DSPs and a RISC core for video compression applications by Stolberg, H.-J., Moch, S., Friebe, L., Dehnhardt, A., Kulaczewski, M.B., Berekovic, M., Pirsch, P.

“…An SoC is comprised of a 16-way SIMD DSP core with a 2D matrix memory, a 64b VLIW DSP core with subword parallelism, and a 32b RISC core. The 81mm/sup 2/ chip…”
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Architectures for multimedia signal processing by Pirsch, P.

“…Architectural concepts are presented aimed at future multimedia processing schemes. Starting from an analysis of current and future multimedia applications,…”
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A video signal processor for MIMD multiprocessing by Hilgenstock, Jörg, Herrmann, Klaus, Otterstedt, Jan, Niggemeyer, Dirk, Pirsch, Peter

“…The video signal processor AxPe1280V has been developed forimplementation of different video coding applications accordingto standards like ITU-T H.261/H.263,…”
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HiBRID-SoC: a multi-core system-on-chip architecture for multimedia signal processing applications by Stolberg, H.-J., Berekovic, M., Friebe, L., Moch, S., Flugel, S., Xun Mao, Kulaczewski, M.B., Klussmann, H., Pirsch, P.

“…The HiBRID-SoC multi-core system-on-chip targets a wide range of application fields with particularly high processing demands, including general signal…”
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Multiprocessor performance for real-time processing of video coding applications by Jeschke, H., Gaedke, K., Pirsch, P.

“…The authors discuss the performance of multiprocessor architectures to be applied for video coding algorithms. SIMD, SIMD cluster, and MIMD architectures are…”
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Realization of a programmable parallel DSP for high performance image processing applications by Wittenburg, Jens Peter, Hinrichs, Willm, Kneip, Johannes, Ohmacht, Martin, Bereković, Mladen, Lieske, Hanno, Kloos, Helge, Pirsch, Peter

“…Architecture and design of the HiPAR-DSP, a SIMD controlled signalprocessor with parallel data paths, VLIW and novel memory design.The processor architecture…”
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Synthetic aperture radar with backprojection: A scalable, platform independent architecture for exhaustive FPGA resource utilization by Cholewa, F., Pfitzner, M., Fahnemann, C., Pirsch, P., Blume, H.

“…This paper introduces a resource-scalable FPGA architecture for backprojection-based stripmap SAR imaging. Low energy consumption and small system dimensions…”
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VLIW architecture optimization for an efficient computation of stereoscopic video applications by Payá-Vayá, G, Martín-Langerwerf, J, Banz, C, Giesemann, F, Pirsch, P, Blume, H

“…This paper presents two new architecture optimizations to improve the processing performance of video applications with a high degree of data parallelism in…”
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Design of a DPCM codec for VLSI realization in CMOS technology by Pirsch, P.

“…Current perspectives on broad-band communication services have made the realization of a DPCM system for video coding on a single integrated circuit…”
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Implementation of a multiprocessor system with distributed embedded DRAM on a large area integrated circuit by Herrmann, K., Moch, S., Hilgenstock, J., Pirsch, P.

“…An architecture of a multiprocessor coding system suitable for large area integration has been developed. Application field is video coding according to the…”
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VLSI chip set for 2D HDTV subband filtering with on-chip line memories by Winzker, M., Gruger, K., Gehrke, W., Pirsch, P.

“…A chip set for 2D subband filtering of HDTV signals has been designed, fabricated and successfully tested. The two chips perform 10*14 quadrature mirror…”
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Adaptive intra-interframe DPCM coder by Pirsch, P.

“…Adaptive prediction schemes provide lower transmission rates than those obtained by simple previous frame prediction. In this paper, we measure the entropy of…”
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