Search Results - "Pilo, H"

An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage by Pilo, H., Barwin, C., Braceras, G., Browning, C., Lamphier, S., Towler, F.

“…This paper describes a 32-Mb SRAM that has been designed and fabricated in a 65-nm low-power CMOS Technology. The 62-mm 2 die features read-assist and…”
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A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reduction by Pilo, H., Adams, C. A., Arsovski, I., Houle, R. M., Lamphier, S. M., Lee, M. M., Pavlik, F. M., Sambatur, S. N., Seferagic, A., Wu, R., Younus, M. I.

“…A 64Mb SRAM is fabricated in a 22nm high-performance SOI technology [1]. The ever-increasing integration needs of complex SoC are driving the reduction of SRAM…”
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An 8 Mb SRAM in 45 nm SOI Featuring a Two-Stage Sensing Scheme and Dynamic Power Management by Ramadurai, V., Pilo, H., Andersen, J., Braceras, G., Gabric, J., Geise, D., Lamphier, S., Yue Tan

“…This paper describes an 8 Mb SRAM test chip that has been designed and fabricated in a 45 nm Silicon-On-Insulator (SOI) CMOS technology. The test chip…”
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A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface by Pilo, H., Anand, D., Barth, J., Burns, S., Corson, P., Covino, J., Lamphier, S.

“…This paper describes a 144-Mb DRAM that operates at a random cycle of 5.6 ns and is capable of producing data rates of 1.4 Gb/s/pin. The 121-mm/sup 2/ die is…”
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An 833-MHz 1.5-W 18-Mb CMOS SRAM with 1.67 Gb/s/pin by Pilo, H., Allen, A., Covino, J., Hansen, P.R., Lamphier, S., Murphy, C., Traver, T., Yee, P.

“…This paper describes an 833-MHz 18-Mb CMOS SRAM with a 1.67-Gb/s/pin data rate. Issues that had to be overcome from previous-generation SRAMs to meet the…”
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An 833MHz 1.5W 18Mb CMOS SRAM with 1.67Gb/s/pin by Pilo, H, Allen, A, Covino, J, Hansen, P, Lamphier, S, Murphy, C, Traver, T, Yee, P

“…An 18 Mb complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) operating at 833MHz was studied. The SRAM was fabricated in a 0.18…”
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Bitline contacts in high density SRAMs: design for testability and stressability by Pilo, H., Adams, R.D., Busch, R.E., Nelson, E.A., Rudgers, G.E.

“…Process scaling and the need for smaller SRAM cells challenges process technologies to make millions of robust and reliable bitline contacts on a single chip…”
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A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements by Pilo, H., Arsovski, I., Batson, K., Braceras, G., Gabric, J., Houle, R., Lamphier, S., Radens, C., Seferagic, A.

“…A 64 Mb SRAM macro has been fabricated in a 32 nm high-k metal-gate SOI technology. The SRAM features a 0.154 μm 2 bit-cell, the smallest to date for a 32 nm…”
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A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements by Pilo, H, Arsovski, I, Batson, K, Braceras, G, Gabric, J, Houle, R, Lamphier, S, Pavlik, F, Seferagic, A, Liang-Yu Chen, Shang-Bin Ko, Radens, C

“…A 64Mb SRAM macro is fabricated in a 32nm high-k metal-gate (HKMG) SOI technology (Greene et al., 2009). Figure 14.1.1 shows the 0.154μm 2 bitcell (BC). A 2x…”
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A 0.9ns random cycle 36Mb network SRAM with 33mW standby power by Pilo, H., Braceras, G., Hall, S., Lamphier, S., Miller, M., Roberts, A., Wistort, R.

“…This paper describes a 36Mb SRAM with an internal random cycle of 0.9ns and is capable of driving and receiving data at 1.1Gb/s/pin on input and output pins…”
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A 550ps Access-Time Compilable SRAM in 65nm CMOS Technology by Wissel, L., Pilo, H., LeBlanc, C., Xiaopeng Wang, Lamphier, S., Fragano, M.

“…A fixed-configuration custom SRAM macro with a highly-scalable architecture was used as the basis for an ASIC SRAM compiler. The 256 Kb fixed-configuration…”
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Design-for-test methods for stand-alone SRAMS at 1Gb/s/pin and beyond by Pilo, Harold, Hansen, Patrick, Lamphier, Steve, Murphy, Chris

“…Design-for-test techniques for wafer test, component test and system-level diagnostics are implemented on stand-alone SRAMs at 1Gb/s/pin. These design-for-test…”
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A 5.6 ns random cycle 144 Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface by Pilo, H., Anand, D., Barth, J., Burns, S., Corson, P., Covino, J., Houghton, R., Lamphier, S.

“…A 144 Mb DRAM operates at a random cycle of 5.6 ns and is capable of producing data rates of 1.4 Gb/s/pin. The 121 mm/sup 2/ die is fabricated in a 0.13 /spl…”
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Design-for-test methods for stand-alone SRAMs at 1 Gb/s/pin and beyond by Pilo, H., Hall, S., Hansen, P., Lamphier, S., Murphy, C.

“…Design-for-test techniques for wafer test, component test and system-level diagnostics are implemented on standalone SRAMs at 1 Gb/s/pin. These design-for-test…”
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An SRAM Design in 65nm and 45nm Technology Nodes Featuring Read and Write-Assist Circuits to Expand Operating Voltage by Pilo, H., Barwin, J., Braceras, G., Browning, C., Burns, S., Gabric, J., Lamphier, S., Miller, M., Roberts, A., Towler, F.

“…This paper describes a 32Mb SRAM that has been designed and fabricated in a 65nm low-power CMOS technology. The design has also been migrated to 45nm bulk and…”
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An 833 MHz 1.5 W 18 Mb CMOS SRAM with 1.67 Gb/s/pin by Pilo, H., Allen, A., Covino, J., Hansen, P., Lamphier, S., Murphy, C., Traver, T., Yee, P.

“…The authors present an 18 Mb CMOS SRAM which operates at 833 MHz with 1.67 Gb/s/pin. The 114.4 mm/sup 2/ die consumes 1.5 W and is fabricated in a 0.18 /spl…”
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A 300 MHz, 3.3 V 1 Mb SRAM fabricated in a 0.5 /spl mu/m CMOS process by Pilo, H., Lamphier, S., Towler, F., Hee, R.

“…A 300 MHz, 1 Mb SRAM with 5.4 ns access in 3.3 V, 0.5 /spl mu/m CMOS uses self-timed and self-resetting circuits. A dual-clock, flow-through read protocol…”
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Embedded memories for the future

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The first auxiliary hospital demonstration by DUJARDIN, J, PILO, H

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