Search Results - "Pesavento, F.L."

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  1. 1

    Measurement of history effect in PD/SOI single-ended CPL circuit by Jenkins, K.A., Puri, R., Chuang, C.T., Pesavento, F.L.

    “…Single-ended complementary pass-transistor logic (CPL), also known as LEAP. has been a popular choice for implementing high-performance arithmetic operations…”
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    Conference Proceeding
  2. 2

    A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing by Lu, N.C.-C., Bronner, G.B., Kitamura, K., Scheuerlein, R.E., Henkels, W.H., Dhong, S.H., Katayama, Y., Kirihata, T., Niijima, H., Franch, R.L., Wang, W., Nishiwaki, M., Pesavento, F.L., Rajeevakumar, T.V., Sakaue, Y., Suzuki, Y., Iguchi, Y., Yano, E.

    Published in IEEE journal of solid-state circuits (01-10-1989)
    “…Describes a 1-Mbit high-speed DRAM (HSDRAM), which has a nominal random access time of less than 27 ns and a column access time of 12 ns with address…”
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    Journal Article
  3. 3

    Characteristics of vertical p-channel MOSFETs for high density circuit application by Wen, D.S., Chang, W.H., Rajeevakumar, T.V., Bronner, G.B., McFarland, P.A., Lii, Y., Chen, T.C., Pesavento, F.L., Manny, M.P., Hwang, W., Dhong, S.H.

    “…Vertical p-channel MOSFETs have been experimentally fabricated and characterized. Device characteristics of vertical p-channel MOSFETs are comparable to those…”
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    Conference Proceeding