Boundary Scan Security Models using Cryptographic Primitives

Various security issues associated with current boundary scan techniques and a new technique to overcome these issues is addressed here. Many of the challenges of the existing systems while enhancing security of testability circuits are modification of logic, area overhead, frequency limitations. He...

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Bibliographic Details
Published in:	2022 6th International Conference on Trends in Electronics and Informatics (ICOEI) pp. 825 - 831
Main Authors:	Paulson, Loyied, Bhakthavatchalu, Ramesh, N, Devika K
Format:	Conference Proceeding
Language:	English
Published:	IEEE 28-04-2022
Subjects:	Cryptography Flip-flops FPGA Hardware Informatics JTAG LFSR Ring oscillators ROPUF Scan Chain Systems operation Xilinx Vivado
Online Access:	Get full text
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Summary:	Various security issues associated with current boundary scan techniques and a new technique to overcome these issues is addressed here. Many of the challenges of the existing systems while enhancing security of testability circuits are modification of logic, area overhead, frequency limitations. Here a secure test wrapper is presented to ensure protection of the internal scan chains along with its primary input and outputs, all of which, can hold important data during system operation. For ensuring security various known cryptographic primitives along with the design are used. The proposed system aims at utilizing the existing components in the design, thus to have less area overhead and to implement strong protection against hardware attacks. This work makes use of Ring Oscillator Physical Unclonnable Function(ROPUF) and higher bit Linear Feedback Shift Register(LFSR) for added protection of the wrapper scan cells and chain. The LFSR is formed by using flip-flops of existing wrapper cells. The entire design and functionality is validated with the help of Xilinx Vivado Tool.
DOI:	10.1109/ICOEI53556.2022.9777228