Search Results - "Paul, Jens"

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  1. 1

    Crack identification and evaluation in BEoL stacks of two different samples utilizing acoustic emission testing and nano X-ray computed tomography by Silomon, Jendrik, Gluch, Jürgen, Clausner, André, Paul, Jens, Zschech, Ehrenfried

    Published in Microelectronics and reliability (01-06-2021)
    “…A novel approach is presented to evaluate the mechanical stability of back end of line (BEoL) stacks. A SRAM test vehicle manufactured in 28 nm technology with…”
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    Journal Article
  2. 2
  3. 3

    Mechanical reliability assessment of 28nm Back End of Line (BEoL) stack using finite element analysis and validation by Machani, Kashi Vishwanath, Geisler, Holm, Breuer, Dirk, Kuechenmeister, Frank, Paul, Jens

    “…In order to address the Chip-Package Interaction (CPI) challenges at an early stage of the product development, GLOBALFOUNDRIES has developed Finite Element…”
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    Conference Proceeding
  4. 4

    Chip Package Interaction (CPI) Stress Modeling by Machani, Kashi Vishwanath, Kuechenmeister, Frank, Breuer, Dirk, Paul, Jens

    “…In order to address the Chip-Package Interaction (CPI) risks associated with advanced silicon packaging, GLOBALFOUNDRIES has developed Finite Element (FE)…”
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    Conference Proceeding
  5. 5

    CPI challenges to BEOL at 28nm node and beyond by Ryan, Vivian, Breuer, D., Geisler, H., Kioussis, D., Lehr, M. U., Paul, J., Machani, K., Shah, Chirag, Kosgalwies, S., Lehmann, L., Jaesik Lee, Kuechenmeister, F., Ryan, E. T., Karimanal, K.

    “…We address package-induced degradation of BEOL interconnects and approaches for recovery. For dielectrics, we cover process options and position in stack for…”
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    Conference Proceeding
  6. 6

    BEoL Damage Evaluation Utilizing Sub-Critical Cu-Pillar Shear Tests, Acoustic Emission, nXCT, and SEM/FIB Analysis by Silomon, Jendrik, Gluch, Jurgen, Posseckardt, Juliane, Clausner, Andre, Paul, Jens, Breuer, Dirk, Zschech, Ehrenfried

    “…In previous works, the resulting damages in the back end of line (BEoL) stack triggered by Copper pillar (Cu-pillar) shear-off events were evaluated and…”
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    Conference Proceeding
  7. 7

    Crack Identification in BEoL Stacks Using Acoustic Emission Testing and Nano X-ray Computed Tomography by Silomon, Jendrik, Gluch, Jurgen, Clausner, Andre, Paul, Jens, Zschech, Ehrenfried

    “…A novel approach is presented to evaluate the mechanical stability of back end of line (BEoL) stacks. A SRAM test vehicle manufactured in 28 nm technology with…”
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    Conference Proceeding
  8. 8

    Reliability Testing of FCCSP Packages for Automotive Applications by Meier, Karsten, Wambera, Laura, Boehme, Bjoern, Goetze, Christian, Capecchi, Simone, Paul, Jens, Wieland, Marcel, Bock, Karlheinz

    “…Autonomous driving and car to car or car to infrastructure communication applications are pursuing and demand for a detailed understanding of the reliability…”
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    Conference Proceeding
  9. 9

    Experiment of 22FDX(R) Chip Board Interaction (CBI) in Wafer Level Packaging Fan-Out (WLPFO) by Cho, Jae Kyu, Paul, Jens, Capecchi, Simone, Kuechenmeister, Frank, Cheng, Ta-Chien

    “…There is growing demand for wafer level packaging, which enables thinner, lighter, and more cost effective packaging solutions. However, these demands come…”
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    Conference Proceeding
  10. 10

    Chip Board Interaction Analysis of 22-NM Fully Depeleted Silicon on Insulator (FD-SOI) Technology in Wafer Level Packaging (WLP) by Cho, Jae Kyu, Paul, Jens, Capecchi, Simone, Breuer, Dirk, Kuechenmeister, Frank, Scott, Doug, Choi, JongJin, Kang, Wonjoon

    “…Recently, Wafer Level Packaging (WLP) has been in high demand, especially in mobile device applications as a path to enable miniaturization while maintaining…”
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    Conference Proceeding
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  12. 12

    Chip package interaction with Cu Pillar interconnects - systematic study of key factors impacting the qualification by Boehme, Bjoern, Breuer, Dirk, Goetze, Christian, Estoque, Al Rhea, Tischer, Falk, Kuechenmeister, Frank, Paul, Jens, Thiele, Michael

    “…Advanced silicon technology nodes are using backend of line (BEOL) stacks consisting of ultra low-k (ULK) materials. ULK materials in combination with Flip…”
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    Conference Proceeding
  13. 13

    Advanced chip package interaction qualification for critical stacks in combination with Cu pillar interconnect technology by Boehme, Bjoern, Goetze, Christian, Dej, Sebastian, Po-Hsiang Wang, Kuechenmeister, Frank, Breuer, Dirk, Paul, Jens, Thiele, Michael

    “…For mobile applications, advanced silicon technology nodes are using Back End Of Line (BEOL) stacks with Ultra Low-k (ULK) materials. Employing these ULK…”
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    Conference Proceeding
  14. 14

    Capital raising by Australian biotechnology IPOs: underpricing, money left and proceeds raised by Paul, Jens, Brooks, Robert, Nicoletti, Gina, Russell, Roslyn

    Published in Accounting research journal (01-01-2006)
    “…The phenomenon of IPO underpricing and issuing companies leaving money on the table is observed across the world. A major issue is around IPO underpricing for…”
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    Journal Article
  15. 15

    TSV integration on 20nm logic Si: 3D assembly and reliability results by Agarwal, Rahul, Hiner, Dave, Kannan, Sukeshwar, KiWook Lee, DoHyeong Kim, JongSik Paek, SungGeun Kang, Yong Song, Dej, Sebastian, Smith, Dan, Thangaraju, Sara, Paul, Jens

    “…Each new technology node brings new design and technology challenges making it harder to maintain Moore's law in a cost effective way. Maintaining cost…”
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    Conference Proceeding
  16. 16

    Chip-package interaction: Challenges and solutions to mechanical stability of Back end of Line at 28nm node and beyond for advanced flip chip application by Kuechenmeister, F., Breuer, D., Geisler, H., Paul, J., Shah, C., Machani, K. V., Kosgalwies, S., Agarwal, R., Gao, S.

    “…Fhis paper discusses the extensive development work carried out by GLOBALFOUNDRIES to mitigate chip-package interaction (CPI) risks for the silicon Backend of…”
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    Conference Proceeding
  17. 17

    Microprobing the mechanical effects of varying dielectric porosity in advanced interconnect structures by Hsing, A., Geisler, H., Ryan, V., Ming Cheng, Machani, K., Breuer, D., Lehr, M. U., Paul, J., Iacopi, F., Dauskardt, R.

    “…Chip-package interaction has become a major concern due to increasingly porous low-K dielectrics. During the packaging process, shear stresses are exerted on…”
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    Conference Proceeding
  18. 18

    CPI assessment using a novel characterization technique based on bump-assisted scratch-indentation testing by Geisler, H., Lehr, M. U., Platz, A., Kuchenmeister, F., Mayer, U., Rossler, T., Paul, J., Lehmann, L., Hofmann, P., Engelmann, H.-J

    “…Integration of compliant and brittle ultralow-k (ULK) interlayer dielectric (ILD) materials in advanced backend-of-line (BEOL) layer stacks requires a careful…”
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    Conference Proceeding
  19. 19

    Aluminium and uptake of base cations by tree roots : a critique of the model proposed by Sverdrup et al by HÖGBERG, P, JENSEN, P

    Published in Water, air, and soil pollution (01-05-1994)
    “…Sverdrup et al. (1992) proposed a model intended to evaluate effects of soil solution (Ca super(2+) + Mg super(2+))/Al super(3+) ratios on the uptake of Ca…”
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    Journal Article
  20. 20

    Uptake of ²⁴Mg by excised pine roots: A preliminary study by Högberg, Peter, Jensén, Paul, Näsholm, Torgny, Ohlsson, Helene

    Published in Plant and soil (01-05-1995)
    “…Uptake of ²⁴Mg by excised roots of Pinus sylvestris L. during up to 4 h long incubations in 99.9 atom % ²⁴Mg (50 µM) was measured by ICP-MS. A rapid initial…”
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    Journal Article