Search Results - "Parthasarthy, C."

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  1. 1

    Physical origin of Vt instabilities in high-k dielectrics and process optimisation by Ribes, G., Bruyere, S., Roy, D., Parthasarthy, C., Muller, M., Denais, M., Huard, V., Skotnicki, T., Ghibaudo, G.

    “…The continuous scaling down of SiO/sub 2/ gate oxide is bound to reach its physical limits owing to gate leakage and reliability concerns. High-k dielectrics…”
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    Conference Proceeding
  2. 2

    Insight on physics of Hf-based dielectrics reliability by Ribes, G., Denais, M., Bruyere, S., Roy, D., Monsieur, F., Huard, V., Parthasarthy, C., Muller, M., Skotnicki, T., Ghibaudo, G.

    “…In this work, we propose an analysis of trapping mechanism and we try to find the possible origins of the traps acting in the BTI stress. In a second section,…”
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    Conference Proceeding
  3. 3

    Novel Positive Bias Temperature Instability (PBTI) of N-Channel Mosfets with Plasma Nitrided Oxide by Huard, V., Guerin, C., Parthasarathy, C.

    “…This work reports for the first time a new positive bias temperature instability (PBTI) degradation mode in n-channel MOSFETs related to the introduction of…”
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    Conference Proceeding
  4. 4

    Origin of Vt instabilities in high-k dielectrics Jahn-Teller effect or oxygen vacancies by Ribes, G., Bruyere, S., Roy, D., Parthasarthy, C., Muller, M., Denais, M., Huard, V., Skotnicki, T., Ghibaudo, G.

    “…In this paper, an analysis of the trapping in high- dielectrics and its origin is given. It is found that the defect is consistent with oxygen vacancies in…”
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    Magazine Article
  5. 5

    Thin oxynitride solution for digital and mixed-signal 65nm CMOS platform by Tavel, B., Bidaud, M., Emonet, N., Barge, D., Planes, N., Brut, H., Roy, D., Vildeuil, J.C., Difrenza, R., Rochereau, K., Denais, M., Huard, V., Llinares, P., Bruyere, S., Parthasarthy, C., Revil, N., Pantel, R., Guyader, F., Vishnubotla, L., Barla, K., Arnaud, F., Stolk, P., Woo, M.

    “…This work shows the benefits of using plasma nitrided gate oxide which supports the gate leakage requirements for 65 nm platform development. Electrical data…”
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    Conference Proceeding