Search Results - "Parrish, J.T."

1 /spl mu/m MOSFET VLSI technology. III. Logic circuit design methodology and applications by Cook, P.W., Schuster, S.E., Parrish, J.T., DiLonardo, V., Freedman, D.R.

“…For pt. II see ibid., vol.SC14, no.2, p.247 (1979). Logic circuits were designed and fabricated in a 1 /spl mu/m silicon-gate MOSFET technology. First,…”
Get full text

1 µm MOSFET VLSI technology: Part III-Logic circuit design methodology and applications by Cook, P.W., Schuster, S.E., Parrish, J.T., DiLonardo, V., Freedman, D.R.

“…Logic circuits were designed and fabricated in a 1 µm silicon-gate MOSFET technology. First, conventional random logic chip images using the largely…”
Get full text

Experimental study of laser formed connections for LSI wafer personalization by Kuhn, L., Schuster, S.E., Zory, P.S., Lynch, G.W., Parrish, J.T.

“…Experimental studies of connections formed in MOS-type structures by nanosecond dye laser pulses are described. Of particular importance are results relating…”
Get full text