Search Results - "Parker, Benjamin D"

Association of Osteocalcin and Abdominal Aortic Calcification in Older Women: The Study of Osteoporotic Fractures by Parker, Benjamin D., Bauer, Douglas C., Ensrud, Kristine E., Ix, Joachim H.

“…Osteocalcin (OC) is produced by osteoblasts and vascular smooth muscle cells. In animal models, serum OC levels are strongly correlated with vascular calcium…”
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The Associations of Fibroblast Growth Factor 23 and Uncarboxylated Matrix Gla Protein With Mortality in Coronary Artery Disease: The Heart and Soul Study by PARKER, Benjamin D, SCHURGERS, Leon J, BRANDENBURG, Vincent M, CHRISTENSON, Robert H, VERMEER, Cees, KETTELER, Markus, SHLIPAK, Michael G, WHOOLEY, Mary A, IX, Joachim H

“…Fibroblast growth factor 23 (FGF23), uncarboxylated matrix Gla protein (ucMGP), and fetuin-A are regulators of mineral metabolism and inhibitors of vascular…”
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Black School Closings Aren’t New: Historically Contextualizing Contemporary School Closings and Black Community Resistance by Morris, Jerome E., Parker, Benjamin D., Negrón, Luimil M.

“…Whereas increased scholarly attention is focusing on contemporary school closings, noticeably absent is the placement of this scholarship within the historical…”
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Integrated Self-Healing for mm-Wave Power Amplifiers by Bowers, S. M., Sengupta, K., Dasgupta, K., Parker, B. D., Hajimiri, A.

“…Self-healing as a technique for improving performance and yield of millimeter-wave power amplifiers (PAs) against process variation and transistor mismatch,…”
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A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing by Sadhu, Bodhisatwa, Ferriss, Mark A., Natarajan, Arun S., Yaldiz, Soner, Plouchart, Jean-Olivier, Rylyakov, Alexander V., Valdes-Garcia, Alberto, Parker, Benjamin D., Babakhani, Aydin, Reynolds, Scott, Li, Xin, Pileggi, Larry, Harjani, Ramesh, Tierno, Jose, Friedman, Daniel

“…This paper describes a new approach to low-phasenoise LC VCO design based on transconductance linearization of the active devices. A prototype 25 GHz VCO based…”
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An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects by Dickson, T. O., Yong Liu, Rylov, S. V., Bing Dang, Tsang, C. K., Andry, P. S., Bulzacchelli, J. F., Ainspan, H. A., Xiaoxiong Gu, Turlapati, L., Beakes, M. P., Parker, B. D., Knickerbocker, J. U., Friedman, D. J.

“…A source synchronous I/O system based on high-density silicon carrier interconnects is introduced. Benefiting from the advantages of advanced silicon packaging…”
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A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology by Bulzacchelli, J.F., Meghelli, M., Rylov, S.V., Rhee, W., Rylyakov, A.V., Ainspan, H.A., Parker, B.D., Beakes, M.P., Aichin Chung, Beukema, T.J., Pepeljugoski, P.K., Shan, L., Kwark, Y.H., Gowda, S., Friedman, D.J.

“…This paper presents a 90-nm CMOS 10-Gb/s transceiver for chip-to-chip communications. To mitigate the effects of channel loss and other impairments, a 5-tap…”
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A 1.8 pJ/bit 16 \times 16\;\text Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration by Dickson, Timothy O., Liu, Yong, Agrawal, Ankur, Bulzacchelli, John F., Ainspan, Herschel A., Toprak-Deniz, Zeynep, Parker, Benjamin D., Beakes, Michael P., Meghelli, Mounir, Friedman, Daniel J.

“…A source-synchronous I/O architecture is reported that includes redundant receiver lanes to enable lane recalibration with reduced power and area overhead. Key…”
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The association of uncarboxylated matrix Gla protein with mitral annular calcification differs by diabetes status: The Heart and Soul study by Parker, Benjamin D, Schurgers, Leon J, Vermeer, Cees, Schiller, Nelson B, Whooley, Mary A, Ix, Joachim H

“…Abstract Objective Mitral annular calcification (MAC) and aortic stenosis (AS) are associated with systemic calcification and cardiovascular disease (CVD)…”
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Association of kidney function and uncarboxylated matrix Gla protein: Data from the Heart and Soul Study by Parker, Benjamin D., Ix, Joachim H., Cranenburg, Ellen C. M., Vermeer, Cees, Whooley, Mary A., Schurgers, Leon J.

“…Background. Vascular calcification is highly prevalent in persons with chronic kidney disease (CKD) and predicts cardiovascular disease (CVD) events. Matrix…”
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Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing" by Sadhu, Bodhisatwa, Ferriss, Mark A., Natarajan, Arun S., Yaldiz, Soner, Plouchart, Jean-Olivier, Rylyakov, Alexander V., Valdes-Garcia, Alberto, Parker, Benjamin D., Babakhani, Aydin, Reynolds, Scott, Li, Xin, Pileggi, Larry, Harjani, Ramesh, Tierno, Jose A., Friedman, Daniel

“…The authors of the above-named article [ibid., vol. 48, no. 5, pp. 1138-1150, May 2013] used a different variable, t B , for the bias tuning knob in equation…”
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W-Band Dual-Polarization Phased-Array Transceiver Front-End in SiGe BiCMOS by Natarajan, Arun, Valdes-Garcia, Alberto, Sadhu, Bodhisatwa, Reynolds, Scott K., Parker, Benjamin D.

“…This paper discusses the design and implementation of a 94-GHz phased-array transceiver front-end in SiGe BiCMOS that is capable of receiving concurrently in…”
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A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons by Seo, J., Brezzo, B., Liu, Y., Parker, B. D., Esser, S. K., Montoye, R. K., Rajendran, B., Tierno, J. A., Chang, L., Modha, D. S., Friedman, D. J.

“…Efforts to achieve the long-standing dream of realizing scalable learning algorithms for networks of spiking neurons in silicon have been hampered by (a) the…”
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A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology by Dickson, Timothy O., Yong Liu, Rylov, Sergey V., Agrawal, Ankur, Seongwon Kim, Ping-Hsuan Hsieh, Bulzacchelli, John F., Ferriss, Mark, Ainspan, Herschel A., Rylyakov, Alexander, Parker, Benjamin D., Beakes, Michael P., Baks, Christian, Lei Shan, Young Kwark, Tierno, Jose A., Friedman, Daniel J.

“…A power-scalable 2 Byte I/O operating at 12 Gb/s per lane is reported. The source-synchronous I/O includes controllable TX driver amplitude, flexible RX…”
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A 1.8 pJ/bit [Formula Omitted] Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration by Dickson, Timothy O, Liu, Yong, Agrawal, Ankur, Bulzacchelli, John F, Ainspan, Herschel A, Toprak-Deniz, Zeynep, Parker, Benjamin D, Beakes, Michael P, Meghelli, Mounir, Friedman, Daniel J

“…A source-synchronous I/O architecture is reported that includes redundant receiver lanes to enable lane recalibration with reduced power and area overhead. Key…”
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A 1.4 pJ/bit, Power-Scalable 1612 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology by Dickson, Timothy O, Liu, Yong, Rylov, Sergey V, Agrawal, Ankur, Kim, Seongwon, Hsieh, Ping-Hsuan, Bulzacchelli, John F, Ferriss, Mark, Ainspan, Herschel A, Rylyakov, Alexander, Parker, Benjamin D, Beakes, Michael P, Baks, Christian, Shan, Lei, Kwark, Young, Tierno, Jose A, Friedman, Daniel J

“…A power-scalable 2 Byte I/O operating at 12 Gb/s per lane is reported. The source-synchronous I/O includes controllable TX driver amplitude, flexible RX…”
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A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS by Plouchart, J.-O., Yaldiz, S., Pileggi, L., Harjani, R., Reynolds, S., Tierno, J. A., Friedman, D., Ferriss, M., Natarajan, A. S., Valdes-Garcia, A., Sadhu, B., Rylyakov, A., Parker, B. D., Beakes, M., Babakhani, A.

“…A 23.5 GHz 32 nm SOI-CMOS PLL with 30% frequency tuning range features an adaptively biased VCO. The adaptive biasing scheme lowers the average PLL power…”
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The Associations of Fibroblast Growth Factor 23 and Uncarboxylated Matrix Gla Protein With Mortality in Coronary Artery Disease: The Heart and Soul Study by Parker, Benjamin D., Schurgers, Leon J., Brandenburg, Vincent M., Christenson, Robert H., Vermeer, Cees, Ketteler, Markus, Shlipak, Michael G., Whooley, Mary A., Ix, Joachim H.

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A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology by Dickson, Timothy O., Yong Liu, Rylov, Sergey V., Agrawal, Ankur, Seongwon Kim, Ping-Hsuan Hsieh, Bulzacchelli, John F., Ferriss, Mark, Ainspan, Herschel, Rylyakov, Alexander, Parker, Benjamin D., Baks, Christian, Lei Shan, Young Kwark, Tierno, Jose, Friedman, Daniel J.

“…A power-scalable 2-Byte I/O operating at 12-Gb/s per lane is reported. The I/O includes controllable TX driver amplitude, flexible RX equalization, and…”
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A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS by Bulzacchelli, J.F., Dickson, T.O., Deniz, Z.T., Ainspan, H.A., Parker, B.D., Beakes, M.P., Rylov, S.V., Friedman, D.J.

“…Extending data rates to meet the I/O needs of future computing and network systems is complicated by limited channel bandwidth. While a DFE can be used to…”
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