Search Results - "Park, Suneui"

A −31dBc integrated-phase-noise 29GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency doubler and injection-locked frequency multipliers by Heein Yoon, Juyeop Kim, Suneui Park, Younghyun Lim, Yongsun Lee, Jooeun Bang, Kyoohyun Lim, Jaehyouk Choi

“…To address the increasing demand for high-bandwidth mobile communications, 5G technology is targeted to support data-rates up to 10Gb/s. To reach this goal,…”
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An extemal-capacitor-less low-dropout regulator with less than −36dB PSRR at all frequencies from 10kHz to 1GHz using an adaptive supply-ripple cancellation technique to the body-gate by Younghyun Lim, Jeonghyun Lee, Suneui Park, Jaehyouk Choi

“…An external capacitor-less low-dropout regulator (LDO) that provides high power-supply rejection ratio (PSRR) at all low-to-high frequencies was presented. The…”
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A 12.24-GHz MDLL With a 102-Multiplication Factor Using a Power-Gating-Based Ring Oscillator by Cho, Yoonseo, Lee, Jeonghyun, Park, Suneui, Yoo, Seyeon, Choi, Jaehyouk

“…This work presents a multiplying delay-locked loop (MDLL) that can generate an ultralow jitter output signal, <inline-formula> <tex-math…”
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An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector by Park, Suneui, Choi, Seojin, Yoo, Seyeon, Cho, Yoonseo, Choi, Jaehyouk

“…This work presents an ultra-low jitter, direct <inline-formula> <tex-math notation="LaTeX">W </tex-math></inline-formula>-band phase-locked loop (PLL). Using…”
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A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68 by Park, Suneui, Yoo, Seyeon, Shin, Yuhwan, Lee, Jeonghyun, Choi, Jaehyouk

“…This work presents an ultralow-jitter ring-oscillator (RO)-based injection-locked clock multiplier (ILCM). Using the power-gating (PG) injection method that…”
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A Low-Jitter Injection-Locked Multi-Frequency Generator Using Digitally Controlled Oscillators and Time-Interleaved Calibration by Yoon, Heein, Park, Suneui, Choi, Jaehyouk

“…This paper presents a low-jitter, injection-locked frequency generator that can provide multiple output frequencies concurrently. The injection-locked…”
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An External Capacitorless Low-Dropout Regulator With High PSR at All Frequencies From 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique by Lim, Younghyun, Lee, Jeonghyun, Park, Suneui, Jo, Yongwoo, Choi, Jaehyouk

“…Herein is presented an external capacitorless low-dropout regulator (LDO) that provides high-power-supply rejection (PSR) at all low-to-high frequencies. The…”
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An ultra-low phase noise all-digital multi-frequency generator using injection-locked DCOs and time-interleaved calibration by Suneui Park, Heein Yoon, Jaehyouk Choi

“…This work presents an ultra-low phase noise and all-digital frequency generator, providing multiple output-frequencies. In a time-interleaved fashion, the…”
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A 0.1-1.5-GHz Wide Harmonic-Locking-Free Delay-Locked Loop Using an Exponential DAC by Park, Suneui, Kim, Juyeop, Hwang, Chanwoong, Park, Hangi, Yoo, Seyeon, Seong, Taeho, Choi, Jaehyouk

“…This letter presents a delay-locked loop (DLL) that can have a wide harmonic-locking-free frequency range, by using a digital-to-analog converter-based…”
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A 122fsrms-Jitter and −60dBc-Reference-Spur 12.24GHz MDLL with a 102 - Multiplication Factor Using a Power-Gating Technique by Cho, Yoonseo, Lee, Jeonghyun, Park, Suneui, Yoo, Seyeon, Choi, Jaehyouk

“…This work presents a low-jitter and high-frequency ring-oscillator (RO)-based multiplying DLL (MDLL). To overcome the limit of conventional MDLLs that use a…”
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4.6 A 47\text}-Jitter and 26.6mW 103.5GHz PLL with Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector and Extended Loop Bandwidth by Bang, Jooeun, Kim, Jaeho, Jung, Seohee, Park, Suneui, Choi, Jaehyouk

“…The W and D bands located at the lower boundary of the sub-THz spectrum are considered viable candidates for CMOS-based wireless-communication systems to…”
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Sub-50-fs RMS Jitter, 103.5-GHz Fundamental-Sampling PLL With an Extended Loop Bandwidth by Bang, Jooeun, Jung, Seohee, Kim, Jaeho, Park, Suneui, Choi, Jaehyouk

“…A sub-THz phase-locked loop (PLL) with a power-gating injection-locked frequency multiplier-based phase detector and extended loop bandwidth was designed to…”
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A 97fsrms-Jitter and 68-Multiplication Factor, 8.16GHz Ring-Oscillator Injection-Locked Clock Multiplier with Power-Gating Injection-Locking and Background Multi-Functional Digital Calibrator by Park, Suneui, Yoo, Seyeon, Shin, Yuhwan, Lee, Jeonghyun, Choi, Jaehyouk

“…To generate low-jitter, high-frequency signals with ring oscillators (ROs), injection-locked clock multipliers (ILCMs) are the most suitable architecture due…”
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23.4 An 82fsrms-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector in 65nm CMOS by Yoo, Seyeon, Park, Suneui, Choi, Seojin, Cho, Yoonseo, Yoon, Heein, Hwang, Chanwoong, Choi, Jaehyouk

“…As the utilization of the mm-wave spectrum becomes active, designers' interests are shifting to even higher frequencies in the W-band. Given their potential…”
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An Ultra-Low Integrated-Phase-Noise 28-GHz LO Generator for 5G Transceivers Supporting Multiple Frequency Bands by Yoon, Heein, Park, Suneui, Kim, Juyeop, Choi, Jaehyouk

“…This work presents a multi-band LO generator that concurrently can support existing cellular bands below 6 GHz and new millimeter-wave (mmW) bands for 5G…”
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An external-capacitor-less high-PSR low-dropout regulator using an adaptive supply-ripple cancellation technique to the body-gate by Lim, Younghyun, Lee, Jeonghyun, Park, Suneui, Choi, Jaehyouk

“…This work presents an external-capacitor-less low-dropout regulator (LDO) that provides high power-supply rejection (PSR) at all low-to-high frequencies. Using…”
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