Search Results - "Park, Hangi"

The Development of Medical Record Items: a User-centered, Bottom-up Approach by Kim, Youngah, Park, Hangi, Kim, Hong-Gee, Kim, Yong Oock

“…Clinical documents (CDs) have evolved from traditional paper documents containing narrative text information into the electronic record sheets composed of…”
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A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector by Park, Hangi, Hwang, Chanwoong, Seong, Taeho, Choi, Jaehyouk

“…This work presents a fractional-<inline-formula> <tex-math notation="LaTeX">N </tex-math></inline-formula> ring-oscillator (RO)-based digital phase-locked loop…”
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A Low-Jitter and Compact-Area Fractional-N Digital PLL With Fast Multi-Variable Calibration Using the Recursive Least-Squares Algorithm by Jang, Seheon, Chae, Munjae, Park, Hangi, Hwang, Chanwoong, Choi, Jaehyouk

“…This work presents a fractional- N digital phase-locked loop (DPLL) characterized by low jitter and small area, featuring fast multi-variable calibration. To…”
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A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM by Hwang, Chanwoong, Park, Hangi, Lee, Yongsun, Seong, Taeho, Choi, Jaehyouk

“…This work presents a low-jitter and low-spur, fractional-<inline-formula> <tex-math notation="LaTeX">N </tex-math></inline-formula> ring-oscillator-based…”
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A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier by Jo, Yongwoo, Kim, Juyeop, Shin, Yuhwan, Park, Hangi, Hwang, Chanwoong, Lim, Younghyun, Choi, Jaehyouk

“…In this work, an ultra-low -jitter wideband cascaded local oscillation (LO) generator for 5G frequency range 1 (FR1) is presented. Using the phase-rotating…”
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A 12.8-15.0-GHz Low-Jitter Fractional- N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation by Kim, Juyeop, Jo, Yongwoo, Park, Hangi, Seong, Taeho, Lim, Younghyun, Choi, Jaehyouk

“…This article presents a low-jitter, low-fractional spur fractional-<inline-formula> <tex-math notation="LaTeX">N</tex-math> </inline-formula> subsampling…”
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An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators by Kim, Juyeop, Lim, Younghyun, Yoon, Heein, Lee, Yongsun, Park, Hangi, Cho, Yoonseo, Seong, Taeho, Choi, Jaehyouk

“…This article presents a cascaded architecture of a frequency synthesizer to generate ultra-low-jitter output signals in a millimeter-wave (mmW) frequency band…”
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10.2 A 5.5μs-Calibration-Time, Low-Jitter, and Compact-Area Fractional-N Digital PLL Using the Recursive-Least-Squares (RLS) Algorithm by Jang, Seheon, Chae, Munjae, Park, Hangi, Hwang, Chanwoong, Choi, Jaehyouk

“…The most common approach for designing a low-jitter PLL is to use a narrow loop bandwidth (BW) to naturally suppress in-band noise, including quantization…”
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A 0.1-1.5-GHz Wide Harmonic-Locking-Free Delay-Locked Loop Using an Exponential DAC by Park, Suneui, Kim, Juyeop, Hwang, Chanwoong, Park, Hangi, Yoo, Seyeon, Seong, Taeho, Choi, Jaehyouk

“…This letter presents a delay-locked loop (DLL) that can have a wide harmonic-locking-free frequency range, by using a digital-to-analog converter-based…”
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A 188fsrms-Jitter and −243d8-FoMjitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector by Hwang, Chanwoong, Park, Hangi, Seong, Taeho, Choi, Jaehyouk

“…Modern SoCs for advanced wireless/wired applications integrate an increasing number of PLLs. 5G TRXs require multiple PLLs to implement complex schemes of…”
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32.1 A 365fsrms-Jitter and -63dBc-Fractional Spur 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC Second/Third- Order Nonlinearity Cancelation and a Probability-Density-Shaping ΔΣM by Park, Hangi, Hwang, Chanwoong, Seong, Taeho, Lee, Yongsun, Choi, Jaehyouk

“…To maximize data-rates by combining more carrier components, 5G RF transceivers require many carrier frequencies, resulting in the situation of many LC PLLs…”
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A 135fsrms-Jitter 0.6-to-7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier by Jo, Yongwoo, Kim, Juyeop, Shin, Yuhwan, Hwang, Chanwoong, Park, Hangi, Choi, Jaehyouk

“…Despite the growing use of mm-wave bands, FR1 bands are still the primary spectrum for 5G communications due to their natural advantages, such as higher…”
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32.4 A 104fsrms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique by Kim, Juyeop, Jo, Yongwoo, Lim, Younghyun, Seong, Taeho, Park, Hangi, Yoo, Seyeon, Lee, Yongsun, Choi, Seojin, Choi, Jaehyouk

“…Subsampling PLLs (SSPLLs) are attractive architectures to generate ultra-low-jitter RF signals due to their intrinsically high phase-error-detection gain, K SH…”
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17.3 A −58dBc-Worst-Fractional-Spur and −234dB-FoMjitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word by Seong, Taeho, Lee, Yongsun, Hwang, Chanwoong, Lee, Jeonghyun, Park, Hangi, Lee, Kyuho Jason, Choi, Jaehyouk

“…Despite their superiority in silicon integration, ring-oscillator-based digital PLLs (RO-DPLLs) are seldom used for mobile transceivers because they have…”
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17.1 A −240dB-FoMjitter and −115dBc/Hz PN @ 100kHz, 7.7GHz Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged Optimally Spaced TDC for Flicker-Noise Reduction by Lee, Yongsun, Seong, Taeho, Lee, Jeonghyun, Hwang, Chanwoong, Park, Hangi, Choi, Jaehyouk

“…Methods to detect and correct timing errors of oscillators are very important to achieve the low-jitter performance of a ring-DCO (RDCO) digital PLL (DPLL). A…”
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17.8 A 170MHz-Lock-In-Range and −253dB-FoMjitter 12-to-14.5GHz Subsampling PLL with a 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator by Lim, Younghyun, Kim, Juyeop, Jo, Yongwoo, Bang, Jooeun, Yoo, Seyeon, Park, Hangi, Yoon, Heein, Choi, Jaehyouk

“…Sub-sampling PLLs (SSPLLs) are popular for generating low-jitter output signals. However, the critical problem of SSPLLs is that they do not use a frequency…”
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