Search Results - "Parekh, Rutu"

Spectral Analysis of Ceres’ Main Linear Features by Andrea Longobardo, Filippo Giacomo Carrozzo, Anna Galiano, Jennifer E. C. Scully, Rutu Parekh, Ernesto Palomba, Maria Cristina De Sanctis, Eleonora Ammannito, Andrea Raponi, Federico Tosi, Mauro Ciarniello, Francesca Zambon, Edoardo Rognini, Maria Teresa Capria, Carol A. Raymond, Christopher T. Russell

“…Linear features are very common on asteroid surfaces. They are generally formed after impact and provide information about asteroid evolution. This work…”
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Single-electron transistor: review in perspective of theory, modelling, design and fabrication by Patel, Rashmit, Agrawal, Yash, Parekh, Rutu

“…Integrated circuit (IC) technology has grown tremendously over the last few decades. The prime goal has been to achieve low-power and high-performance in logic…”
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An overview of explosive volcanism on Mars by Brož, Petr, Bernhardt, Hannes, Conway, Susan J., Parekh, Rutu

“…Decades of space exploration reveal that Mars has been reshaped by volcanism throughout its history. The range of observed volcanic landforms shows that…”
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Design strategy and simulation of single-gate SET for novel SETMOS hybridization by Shah, Raj, Parekh, Rutu, Dhavse, Rasika

“…This paper presents a design methodology for a single-gate single-electron transistor (SG-SET) for room temperature operation of SET and hybrid SETMOS…”
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Structure Fortification of Mixed CNT Bundle Interconnects for Nano Integrated Circuits Using Constraint-Based Particle Swarm Optimization by Pathade, Takshashila, Agrawal, Yash, Parekh, Rutu, Kumar, Mekala Girish

“…The emerging VLSI technology and simultaneously highly dense packaging of devices and interconnects in nano-scale chips have prosperously enabled realization…”
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Evaluating Volatile Induced Surface Features on Vesta and Ceres by Parekh, Rutu

“…This work evaluates volatile induced surface features on Vesta and Ceres, two of the largest asteroids present within the asteroid belt. Both the planetary…”
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Signal integrity analysis of bundled carbon nanotubes as futuristic on-chip interconnects by Pathade, Takshashila, Agrawal, Yash, Parekh, Rutu, Palaparthy, Vinay

“…Rigorous technology scaling of integrated circuits to nanometer range aids to acquire prodigious operational speed and versatile functionality in…”
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Design and implementation of single electron transistor based 8X8 bit signed multipliers by Shah, Chintan, Shah, Raj, Dhavse, Rasika, Parekh, Rutu

“…Single electron transistor (SET) has several advantages over CMOS such as it is highly scalable and has ultra-low power consumption. It has emerged as a…”
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Simulation and Design Methodology for Hybrid SET-CMOS Integrated Logic at 22-nm Room-Temperature Operation by Parekh, R., Beaumont, A., Beauvais, J., Drouin, D.

“…Single-electron transistor (SET) circuits can be stacked above the CMOS platform to achieve functional and heterogeneous 3-D integration of nanoelectronic…”
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Influence of Volatiles on Mass Wasting Processes on Vesta and Ceres by Parekh, R., Otto, K. A., Jaumann, R., Matz, K. D., Roatsch, T., Kersten, E., Elgner, S., Raymond, C.

“…We have analyzed mass wasting features, their distribution and deposit geometry on the two largest main asteroid belt objects—protoplanet Vesta and dwarf…”
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ASIC Chip Design For Healthcare System by Nathwani, Nishit, Patel, Rupali, Parekh, Rutu

“…This paper presents an Application-Specific Integrated Circuit (ASIC) implementation suitable for healthcare applications that employ RISC-V as a digital…”
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Formation of Ejecta and Dust Pond Deposits on Asteroid Vesta by Parekh, R., Otto, K. A., Matz, K. D., Jaumann, R., Krohn, K., Roatsch, T., Kersten, E., Elgner, S., Russell, C. T., Raymond, C. A.

“…Dust and melt ponds have been studied on planetary bodies including Eros, Itokawa, and the Moon. However, depending on the nature of the regolith material…”
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On-Board Diagnostics based remote emission test for Light Motor Vehicles by Rajput, Pruthvish, Parekh, Rutu

“…Electronics is becoming an indispensable part of vehicular technology. With the advancement in vehicular technology, on-board diagnostics (OBD) emission checks…”
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ASIC SoC Design for Edge Computing Agriculture Application by Pandya, Abhishek, Agrawal, Radhika, Panchal, Viraj, Parekh, Rutu

“…This paper introduces an ASIC implementation tailored for agriculture applications, leveraging RISC-V for digital processing and sensor interfacing circuits…”
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RTL & Physical Design Flow of Power Efficient Components of All Digital Phase Locked Loop (ADPLL) by Joshi, Aaditya, Nathwani, Nishit, Parekh, Rutu

“…In this paper, the physical design (PD) of components of an all-digital based low power phase-locked loop is proposed. Open-source EDA tools are used to…”
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RTL to GDSII Implementation of RADIX-4 Booth Multiplier by Gaurav, Tanya, Patel, Krutarthkumar, Parekh, Rutu

“…Booth Multiplier is widely used for high performance signed multiplication by several encoding schemes. Due to the faster generation of partial product, the…”
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DNA Based Hybrid Circuit Design Approaches by Patel, Rashmit, Parekh, Rutu

“…The present VLSI technology faces challenges like power density, design optimization, fabrication cost etc. The VLSI design is carried out using design entry,…”
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Simulation and design methodology for hybrid SET-CMOS logic at room temperature operation by Parekh, Rutu

“…The purpose of this thesis is to research the possibility of realizing hardware support for hybrid single electron transistor (SET)-CMOS circuits by a…”
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Implementation and Physical Design of 8/4-Bit Signed Divider by Purohit, Shubham, Laddha, Prashant, Parekh, Rutu

“…This paper focuses on implementing a signed binary divider using Verilog and performing a physical design process i.e. register transfer level (RTL) to graphic…”
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Design and Implementation of low power RISC V ISA based coprocessor design for Matrix multiplication by Gaurav, Tanya, Bhatt, Amit, Parekh, Rutu

“…RISC V is an open-source ISA that is used to design the processor and the coprocessor architecture. For fulfilling the requirement of matrix multiplication, a…”
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