Search Results - "Panicker, Rajesh C."

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  1. 1

    Low Power Optimisations for IoT Wearable Sensors Based on Evaluation of Nine QRS Detection Algorithms by Li, Jiamin, Ashraf, Adnan, Cardiff, Barry, Panicker, Rajesh C., Lian, Yong, John, Deepu

    “…This paper aims to reduce the power consumption of electrocardiography based wearable healthcare devices, by introducing power reduction approaches and…”
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    Journal Article
  2. 2

    Binary Classifiers for Data Integrity Detection in Wearable IoT Edge Devices by John, Arlene, Panicker, Rajesh C., Cardiff, Barry, Lian, Yong, John, Deepu

    “…This paper presents a comparison of several artificial intelligence (AI) based binary classifiers for detecting the integrity of data obtained from Internet of…”
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    Journal Article
  3. 3

    An Asynchronous P300 BCI With SSVEP-Based Control State Detection by Panicker, Rajesh C., Puthusserypady, Sadasivan, Sun, Ying

    “…In this paper, an asynchronous brain-computer interface (BCI) system combining the P300 and steady-state visually evoked potentials (SSVEPs) paradigms is…”
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    Journal Article
  4. 4

    Project-Based Learning in Embedded Systems Education Using an FPGA Platform by Kumar, Akash, Fernando, Shakith, Panicker, Rajesh C.

    Published in IEEE transactions on education (01-11-2013)
    “…With embedded systems becoming ubiquitous, there is a growing need to teach and train engineers to be well-versed in their design and development. The…”
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    Journal Article
  5. 5

    RISCALAR: A Cycle-Approximate, Parametrisable RISC-V Microarchitecture Explorer & Simulator by Mendes, Josiah, Panicker, Rajesh C.

    “…Riscalar is a highly parameterisable, extensible, and modular computer architecture simulation tool designed for the RISC-V ISA. The ability of Riscalar to…”
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    Conference Proceeding
  6. 6

    Fully Remote Project-Based Learning of Hardware/Software Codesign by Panicker, Rajesh C, John, Deepu

    “…This Innovative Practice Category Work-In-Progress paper describes the innovative way in which a course on hardware/software codesign was conducted fully…”
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    Conference Proceeding
  7. 7

    Introducing FPGA-based Machine Learning on the Edge to Undergraduate Students by Panicker, Rajesh C, Kumar, Akash, John, Deepu

    “…This innovative practice category work in progress paper describes a project in a final-year un-dergraduate course on implementing a neural accelerator on an…”
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    Conference Proceeding
  8. 8

    Adaptation in P300 Brain-Computer Interfaces: A Two-Classifier Cotraining Approach by Panicker, Rajesh C., Puthusserypady, Sadasivan, Sun, Ying

    “…A cotraining-based approach is introduced for constructing high-performance classifiers for P300-based brain-computer interfaces (BCIs), which were trained…”
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    Journal Article
  9. 9

    Exposing Students to a State-of-the-art Problem Through a Capstone Project by Panicker, Rajesh C, Sasidhar, Sangit, Jien, Soo Yuen, Keng-Yan Tan, Colin

    “…This Innovative Practice category Full Paper presents the use of a state-of-the-art research problem for a capstone project for third year computer engineering…”
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    Conference Proceeding
  10. 10

    Multistage Pruning of CNN Based ECG Classifiers for Edge Devices by Xiaolin, Li, Panicker, Rajesh C., Cardiff, Barry, John, Deepu

    “…Using smart wearable devices to monitor patients' electrocardiogram (ECG) for real-time detection of arrhythmias can significantly improve healthcare outcomes…”
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    Conference Proceeding Journal Article
  11. 11

    Binary ECG Classification Using Explainable Boosting Machines for IoT Edge Devices by Xiaolin, Li, Qingyuan, Wang, Panicker, Rajesh C., Cardiff, Barry, John, Deepu

    “…This paper presents an explainable, low-complexity binary electrocardiogram (ECG) classifier to be deployed in a resource-limited wearable edge device. The…”
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    Conference Proceeding
  12. 12

    Classification of ECG based on Hybrid Features using CNNs for Wearable Applications by Xiaolin, Li, Xiang, Fang, Panicker, Rajesh C., Cardiff, Barry, John, Deepu

    “…Sudden cardiac death and arrhythmia account for a large percentage of all deaths worldwide. Electrocardiography (ECG) is the most widely used screening tool…”
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    Conference Proceeding
  13. 13

    Atrial Fibrillation Detection Using Weight-Pruned, Log-Quantised Convolutional Neural Networks by Chang, Xiu Qi, Chew, Ann Feng, Choong, Benjamin Chen Ming, Wang, Shuhui, Han, Rui, He, Wang, Xiaolin, Li, Panicker, Rajesh C., John, Deepu

    “…Deep neural networks (DNN) are a promising tool in medical applications. However, the implementation of complex DNNs on battery-powered devices is challenging…”
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    Conference Proceeding
  14. 14

    Classification of ECG based on Hybrid Features using CNNs for Wearable Applications by Xiaolin, Li, Xiang, Fang, Panicker, Rajesh C, Cardiff, Barry, John, Deepu

    Published 14-06-2022
    “…Sudden cardiac death and arrhythmia account for a large percentage of all deaths worldwide. Electrocardiography (ECG) is the most widely used screening tool…”
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    Journal Article
  15. 15

    Adaptive Learning and Analytics in Engineering Education by Panicker, Rajesh C., Kumar, Akash, Srinivasan, Dipti, John, Deepu

    “…The fact that different students have different ability levels and learning patterns limit the effectiveness of traditional one-size-fits-all classroom-based…”
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    Conference Proceeding
  16. 16

    Atrial Fibrillation Detection Using Weight-Pruned, Log-Quantised Convolutional Neural Networks by Chang, Xiu Qi, Chew, Ann Feng, Choong, Benjamin Chen Ming, Wang, Shuhui, Han, Rui, He, Wang, Xiaolin, Li, Panicker, Rajesh C, John, Deepu

    Published 14-06-2022
    “…Deep neural networks (DNN) are a promising tool in medical applications. However, the implementation of complex DNNs on battery-powered devices is challenging…”
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    Journal Article
  17. 17

    Acceleration of genetic algorithm based FPGA placers using GPGPU by Cheong, Ke You, Panicker, Rajesh C.

    Published in 2016 IEEE Region 10 Conference (TENCON) (01-11-2016)
    “…With the scaling of process nodes, the complexity of IC design continues to increase. This increase in complexity greatly increases the time needed by many…”
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    Conference Proceeding
  18. 18

    ProcGen - a framework for learning computer architecture by Thangavel, Dinesh, Panicker, Rajesh C., Veeravalli, Bharadwaj

    Published in 2016 IEEE Region 10 Conference (TENCON) (01-11-2016)
    “…Students in intermediate hardware design courses face a number of difficulties while designing and implementing complex circuits using Hardware Description…”
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    Conference Proceeding
  19. 19

    Enhancing VHDL learning through a light-weight integrated environment for development and automated checking by Kumar, Akash, Panicker, Rajesh C., Kassim, Ashraf

    “…The development environments for Hardware Description Languages (HDLs) are essentially meant and designed for highly trained professionals/ engineers and as…”
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    Conference Proceeding
  20. 20

    Development of an FPGA-based real-time P300 speller by Khurana, K., Gupta, P., Panicker, R. C., Kumar, A.

    “…A Brain Computer Interface (BCI) is a system that allows direct communication between a computer and the human brain. Though the main application for BCIs is…”
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    Conference Proceeding