Search Results - "Pangal, A."

A 28.5GB/s CMOS non-blocking router for terabits/s connectivity between multiple processors and peripheral I/O nodes by Nair, R, Borkar, N Y, Browning, C S, Dermer, G E, Erraguntla, V, Govindarajulu, V, Pangal, A, Prijic, J D, Rankin, L, Seligman, E, Vangal, S, Wilson, H A

“…A 28.5GB/s complementary metal oxide semiconductor (CMOS) non-blocking router was proposed for a mixed high bandwidth processor and low-speed input/output…”
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5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS by Vangal, S, Anders, M.A, Borkar, N, Seligman, E, Govindarajulu, V, Erraguntla, V, Wilson, H, Pangal, A, Veeramachaneni, V, Tschanz, J.W, Ye, Y, Somasekhar, D, Bloechel, B.A, Dermer, G.E, Krishnamurthy, R.K, Soumyanath, K, Mathew, S, Narendra, S.G, Stan, M.R, Thompson, S, De, V, Borkar, S

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5-GHz 32-bit integer execution core in 130-nm dual-V/T/ CMOS by Vangal, S, Anders, M A, Borkar, N, Seligman, E, Govindarajulu, V, Erraguntla, V, Wilson, H, Pangal, A, Veeramachaneni, V, Tschanz, J W, Ye, Y, Somasekhar, D, Bloechel, B A, Dermer, G E, Krishnamurthy, R K, Soumyanath, K, Mathew, S, Narendra, S G, Stan, M R

“…A 32-bit integer execution core containing a Han-Carlson arithmetic-logic unit (ALU), an 8-entry x 2 ALU instruction scheduler loop and a 32-entry x 32-bit…”
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5-GHz 32-bit integer execution core in 130-nm dual-V/sub T/ CMOS by Vangal, S., Anders, M.A., Borkar, N., Seligman, E., Govindarajulu, V., Erraguntla, V., Wilson, H., Pangal, A., Veeramachaneni, V., Tschanz, J.W., Ye, Y., Somasekhar, D., Bloechel, B.A., Dermer, G.E., Krishnamurthy, R.K., Soumyanath, K., Mathew, S., Narendra, S.G., Stan, M.R., Thompson, S., De, V., Borkar, S.

“…A 32-bit integer execution core containing a Han-Carlson arithmetic-logic unit (ALU), an 8-entry /spl times/ 2 ALU instruction scheduler loop and a 32-entry…”
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5-GHz 32-bit integer execution core in 130-nm dual-V sub(T) CMOS by Vangal, S, Anders, MA, Borkar, N, Seligman, E, Govindarajulu, V, Erraguntla, V, Wilson, H, Pangal, A, Veeramachaneni, V, Tschanz, J W, Ye, Y, Somasekhar, D, Bloechel, BA, Dermer, GE, Krishnamurthy, R K, Soumyanath, K, Mathew, S, Narendra, S G, Stan, M R, Thompson, S, De, V, Borkar, S

“…A 32-bit integer execution core containing a Han-Carlson arithmetic-logic unit (ALU), an 8-entry 2 ALU instruction scheduler loop and a 32-entry 32-bit…”
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A 2 5 GHz 32 b integer-execution core in 130 nm dual-V sub(T) CMOS by Vangal, S, Borkar, N, Seligman, E, Govindarajulu, V, Erraguntla, V, Wilson, H, Pangal, A, Veeramachaneni, V, Anders, M, Tschanz, J, Ye, Y, Somasekhar, D, Bloechel, B, Dermer, G, Krishnamurthy, R

“…A discussion on a 25 GHz 32b integer-execution core in 130nm dual-V sub(T) CMOS is presented. The architecture of the system consists of three first in first…”
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5 GHz 32 b integer-execution core in 130 nm dual-V sub(T) CMOS by Vangal, S, Borkar, N, Seligman, E, Govindarajulu, V, Erraguntla, V, Wilson, H, Pangal, A, Veeramachaneni, V, Anders, M, Tschanz, J, Ye, Y, Somasekhar, D, Bloechel, B, Dermer, G, Krishnamurthy, R

“…A 32 b integer execution core implements 12 instructions. Circuit and body bias techniques together increase the core clock frequency to 5 GHz. In a 130 nm…”
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A 28.5 GB/s CMOS non-blocking router for terabit/s connectivity between multiple processors and peripheral I/O nodes by Nair, R., Borkar, N.Y., Browning, C.S., Dermer, G.E., Eriaguntla, V., Govindarajulu, V., Pangal, A., Prijic, J.D., Rankin, L., Seligman, E., Vangal, S., Wilson, H.A.

“…A 28.5 GB/s data router enables a terabits/s bandwidth network. The 6.6M transistor 0.18 /spl mu/m 1.3 V 15 W CMOS LSI has three clocking domains that…”
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1.1V 1GHz communications router with on-chip body bias in 150nm CMOS by Narendra, S., Haycock, M., Govindarajulu, V., Erraguntla, V., Wilson, H., Vangal, S., Pangal, A., Seligman, E., Nair, R., Keshavarzi, A., Bloechel, B., Dermer, G., Mooney, R., Borkar, N., Borkar, S., Vivek De

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1.1 V 1 GHz communications router with on-chip body bias in 150 nm CMOS by Narendra, S., Haycock, M., Govindarajulu, V., Erraguntla, V., Wilson, H., Vangal, S., Pangal, A., Seligman, E., Nair, R., Keshavarzi, A., Bloechel, B., Dermer, G., Mooney, R., Borkar, N., Borkar, S., De, V.

“…A router chip, that incorporates on-chip forward body biasing capability with 2% area overhead, achieves 1 GHz operation at 1.1 V supply in a 150 nm logic…”
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A 25 GHz 32 b integer-execution core in 130 nm dual-V/sub T/ CMOS by Vangal, S., Borkar, N., Seligman, E., Govindarajulu, V., Erraguntla, V., Wilson, H., Pangal, A., Veeramachaneni, V., Anders, M., Tschanz, J., Ye, Y., Somasekhar, D., Bloechel, B., Dermer, G., Krishnamurthy, R., Narendra, S., Stan, M., Thompson, S., De, V., Borkar, S.

“…A 32 b integer execution core implements 12 instructions. Circuit and body bias techniques together increase the core clock frequency to 5 GHz. In a 130 nm…”
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5GHz 32b integer-execution core in 130nm dual-V/sub T/ CMOS by Vangal, S., Borkar, N., Seligman, E., Govindarajulu, V., Erraguntla, V., Wilson, H., Pangal, A., Veeramachaneni, V., Anders, M., Tschanz, J., Ye, Y., Somasekhar, D., Bloechel, B., Dermer, G., Krishnamurthy, R., Narendra, S., Stan, M., Thompson, S., De, V., Borkar, S.

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中性粒细胞与淋巴细胞比值对伴随前葡萄膜炎的Behet病的影响 by Avci Atil Avci Deniz Cinar Salih Levent Cetinkaya Ali Karahan Samet Erden Abdulsamet Ozyurt Kemal Ulas Yilmaz Ertas Ragip Pangal Emine

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Pentacam Scheimpflug成像测量晶状体密度与torsional超声乳化参数间的关系 by Suleyman Demircan Mustafa Atas Murat Koksal Emine Pangal Isa Yuvaci Altan Goktas

“…目的：评价运用Pentacam Scheimpflug成像测量晶状体核密度与torsinal超声乳化动力学参数（如：运用于老年核性白内障患者的超声能量水平、液体留存时间及液体量）间的关系。方法：此研究为前瞻性双盲研究。瞳孔扩大后运用Pentacam Scheimpflug…”
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