Search Results - "Pandya, Paritosh K."

Specification and Optimal Reactive Synthesis of Run-time Enforcement Shields by Pandya, Paritosh K., Wakankar, Amol

“…A system with sporadic errors (SSE) is a controller which produces high quality output but it may occasionally violate a critical requirement REQ(I,O). A…”
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Two-variable logics with some betweenness relations: Expressiveness, satisfiability and membership by Andreas Krebs, Kamal Lodaya, Paritosh K. Pandya, Howard Straubing

“…We study two extensions of FO2[<], first-order logic interpreted in finite words, in which formulas are restricted to use only two variables. We adjoin to this…”
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Deterministic Temporal Logics and Interval Constraints by Lodaya, Kamal, Pandya, Paritosh K.

“…In temporal logics, a central question is about the choice of modalities and their relative expressive power, in comparison to the complexity of decision…”
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Specification and optimal reactive synthesis of run-time enforcement shields by Pandya, Paritosh K., Wakankar, Amol

“…A run time enforcement shield is a controller which corrects the output O of a system with sporadic errors (SSE) so as to guarantee the invariance of a…”
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Partially Punctual Metric Temporal Logic is Decidable by Madnani, Khushraj, Krishna, Shankara Narayanan, Pandya, Paritosh K.

“…Metric Temporal Logic MTL[U I , S I ] is one of the most studied real time logics. It exhibits considerable diversity in expressiveness and decidability…”
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Specification and Optimal Reactive Synthesis of Run-time Enforcement Shields by Pandya, Paritosh K, Wakankar, Amol

“…EPTCS 305, 2019, pp. 91-106 A system with sporadic errors (SSE) is a controller which produces high quality output but it may occasionally violate a critical…”
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Specification and Reactive Synthesis of Robust Controllers by Pandya, Paritosh K, Wakankar, Amol

“…This paper investigates the synthesis of robust controllers from logical specification of regular properties given in an interval temporal logic QDDC. Our…”
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Satisfiability Checking of Multi-Variable TPTL with Unilateral Intervals Is PSPACE-Complete by Krishna, Shankara Narayanan, Madnani, Khushraj Nanik, Majumdar, Rupak, Pandya, Paritosh K

“…We investigate the decidability of the ${0,\infty}$ fragment of Timed Propositional Temporal Logic (TPTL). We show that the satisfiability checking of…”
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Generalizing Non-Punctuality for Timed Temporal Logic with Freeze Quantifiers by Krishna, Shankara Narayanan, Madnani, Khushraj, MazoJr, Manuel, Pandya, Paritosh K

“…Metric Temporal Logic (MTL) and Timed Propositional Temporal Logic (TPTL) are prominent real-time extensions of Linear Temporal Logic (LTL). In general, the…”
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DCSYNTH: Guided Reactive Synthesis with Soft Requirements by Wakankar, Amol, Pandya, Paritosh K, Matteplackel, Rajmohan

“…In reactive controller synthesis, a number of implementations (controllers) are possible for a given specification because of the incomplete nature of…”
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Two-variable logics with some betweenness relations: Expressiveness, satisfiability and membership by Krebs, Andreas, Lodaya, Kamal, Pandya, Paritosh K, Straubing, Howard

“…Logical Methods in Computer Science, Volume 16, Issue 3 (September 8, 2020) lmcs:5206 We study two extensions of FO2[<], first-order logic interpreted in…”
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Deterministic Temporal Logics and Interval Constraints by Lodaya, Kamal, Pandya, Paritosh K

“…EPTCS 243, 2017, pp. 23-40 In temporal logics, a central question is about the choice of modalities and their relative expressive power, in comparison to the…”
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Logics Meet 2-Way 1-Clock Alternating Timed Automata by Krishna, Shankara Narayanan, Madnani, Khushraj Nanik, MazoJr, Manuel, Pandya, Paritosh K

“…In this paper, we study the extension of 1-clock Alternating Timed Automata (1-ATA) with the ability to read in both forward and backward direction, the 2-Way…”
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DCSYNTH: Guided Reactive Synthesis with Soft Requirements for Robust Controller and Shield Synthesis by Wakankar, Amol, Pandya, Paritosh K, Matteplackel, Raj Mohan

“…DCSYNTH is a tool for the synthesis of controllers from safety and bounded liveness requirements given in interval temporal logic QDDC. It investigates the…”
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Formalizing Timing Diagram Requirements in Discrete Duration Calulus by Matteplackel, Raj Mohan, Pandya, Paritosh K, Wakankar, Amol

“…Several temporal logics have been proposed to formalise timing diagram requirements over hardware and embedded controllers. These include LTL, discrete time…”
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Deterministic Logics for UL by Pandya, Paritosh K, Shah, Simoni S

“…The class of Unambiguous Star-Free Regular Languages (UL) was defined by Schutzenberger as the class of languages defined by Unambiguous Polynomials. UL has…”
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Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts by Mohalik, Swarup, Rajeev, A. C., Dixit, Manoj G., Ramesh, S., Suman, P. Vijay, Pandya, Paritosh K., Jiang, Shengbing

“…End-to-end latency of messages is an important design parameter that needs to be within specified bounds for the correct functioning of distributed real-time…”
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The Unary Fragments of Metric Interval Temporal Logic: Bounded versus Lower bound Constraints (Full Version) by Pandya, Paritosh K, Shah, Simoni S

“…Proc. ATAV 2012, LNCS 7561, 2012. pp 77-91 We study two unary fragments of the well-known metric interval temporal logic MITL[U_I,S_I] that was originally…”
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Finding Extremal Models of Discrete Duration Calculus formulae using Symbolic Search by Pandya, Paritosh K.

“…QDDC is a logic for specifying quantitative timing aspects of synchronous programs. Properties such as worst-case response time and latency (when known) can be…”
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Interval Duration Logic: Expressiveness and Decidability by Pandya, Paritosh K.

“…We investigate a variant of dense-time Duration Calculus which permits model checking using timed/hybrid automata. We define a variant of the Duration…”
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