Search Results - "Pandey, Shesh Mani"

An Extrinsic Device and Leakage Mechanism in Advanced Bulk FinFET SRAM by Mann, Randy W., Zhao, Meixiong, Parihar, Sanjay, Gao, Qun, Arya, Ankur, Radens, Carl, Pandey, Shesh Mani, Versaggi, Joseph, Higman, Jack M., Carter, Rick

“…A previously unrecognized vertical-extrinsic device in advanced 7-nm FinFET SRAM structures is identified and characterized for the first time. The ON-current…”
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Extraction of parasitic and channel resistance components in FinFETs using TCAD tools by Narayanan, Sudarshan, Banghart, Edmund, Zeitzoff, Peter, Korablev, Konstantin, Pandey, Shesh Mani, Gendron-Hansen, Amaury, Benistant, Francis

“…•Practical method to extract channel and parasitic resistance in a FinFET device.•Useful guide in designing FinFETs with minimized parasitic…”
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High performance 0.1μm CMOS device with suppressed parasitic junction capacitance and junction leakage current by HYUN SIK KIM, SHIANG YANG ONG, SARKAR, Manju, YOUNG WAY TEH, SHESH MANI PANDEY, BENISTANT, Francis, QUEK, Elgin, BHAT, Mousumi, CHU, Sanford

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Impact of additional LDD rapid thermal annealing on submicron n-MOSFETs by Qian Wensheng, Leong, V.K.W., Wang Yuwen, Li Yisuo, Pandey Shesh Mani, Manju, S., Benistant, F., Chu, S.

“…An additional NLDD Rapid Thermal Annealing (RTA) had been implemented in thin-gate and thick-gate NMOS transistors. The threshold voltage (Vt) distribution at…”
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Influence of stress induced CT local layout effect (LLE) on 14nm FinFET by Pei Zhao, Pandey, Shesh Mani, Banghart, Edmund, Xiaoli He, Asra, Ram, Mahajan, Vinayak, Haojun Zhang, Baofu Zhu, Yamada, Kenta, Linjun Cao, Balasubramaniam, Pala, Joshi, Manoj, Eller, Manfred, Benistant, Francis, Samavedam, Srikanth

“…In this paper, we present a new local layout effect in 14nm FinFET due to different CT layout designs (CT extension, CT spacing, and PC past RX distance)…”
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Methodology to achieve planar technology-like ESD performance in FINFET process by Jian-Hsing Lee, Prabhu, Manjunatha, Korablev, Konstantin, Singh, Jagar, Natarajan, Mahadeva Iyer, Pandey, Shesh Mani

“…Method for making Finfet ESD performance comparable to bulk planar ESD devices is demonstrated using a simple but effective process. Low FIN silicon volume…”
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Contact model based on TCAD-experimental interactive algorithm by Feng, Peijie, Kim, Jiseok, Cho, Jin, Pandey, Shesh Mani, Narayanan, Sudarshan, Tng, Michelle, Liu, Bingwu, Banghart, Edmund, Zhu, Baofu, Zhao, Pei, Rahman, Muhammad, Park, Yumi, Jiang, Liu, Benistant, Francis

“…This work demonstrated a novel method utilizing Sentaurus Technology Computer Aided Design simulation along with experiments to intermediately extract Schottky…”
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Analog, RF, and ESD device challenges and solutions for 14nm FinFET technology and beyond by Singh, Jagar, Jerome, Ciavatti, Wei, Andy, Miller, Roderick, Arnaud, Bousquet, Lili, Cheng, Hui Zang, Kasun, Punchihewa, Manjunatha, Prabhu, Biswanath, Senapati, Kumar, Anil, Pandey, Shesh Mani, Iyer, Natarajan M., Mittal, Anurag, Carter, Rick, Lun Zhao, Manfred, Eller, Samavedam, Srikanth

“…Fin-based analog, passive, RF and ESD devices have serious performance challenges, such as poor ideality, higher leakage, low breakdown voltage (BV) of diodes,…”
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Impact of STI stress on hot carrier degradation in 5V NMOSFET by Hao Jiang, Hin Kiong Yap, Pandey, S. M., Jae Soo Park, Lim, J., Xu Zeng

“…The effects of shallow trench isolation (STI) induced mechanical stress on hot carrier degradation of 5V NMOSFET with different source(S)/drain(D) areas are…”
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Enhanced nFinFET ESD performance by Jian-Hsing Lee, Prabhu, Manjunatha, Iyer, Natarajan Mahadeva, Banghart, Edmund, You Li, Ronghua Yu, Poro, Richard, Hogle, Nicholas, Gebreselaie, Ephrem, Pandey, Shesh Mani, Gauthier, Robert

“…A very simple and useful scheme to enhance the ESD performance of the nFinFET is proposed. By incorporating the N-Well (NW) with the nFinFET, it becomes a low…”
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Investigation of performance limiting factors of sub-10nm III-V FinFETs by Peijie Feng, Narayanan, Sudarshan, Pandey, Shesh Mani, Sahu, Bhagawan, Benistant, Francis, Towie, Ewan, Alexander, Craig, Amoroso, Salvatore M., Asenov, Asen

“…As scaling of transistor continues, there is strong impetus to replace Si with attractive alternate channel materials like InGaAs that would provide high…”
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