Search Results - "Pagliarini, Samuel N."

A Probabilistic Synapse With Strained MTJs for Spiking Neural Networks by Pagliarini, Samuel N., Bhuin, Sudipta, Isgenc, Mehmet Meric, Biswas, Ayan Kumar, Pileggi, Larry

“…Spiking neural networks (SNNs) are of interest for applications for which conventional computing suffers from the nearly insurmountable memory-processor…”
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From Virtual Characterization to Test-Chips: DFM Analysis Through Pattern Enumeration by Martins, Mayler G. A., Pagliarini, Samuel N., Isgenc, Mehmet Meric, Pileggi, Larry

“…As CMOS technology continues to scale down due to advances in lithography, the interaction of neighboring patterns is exacerbated. Every pattern printed on…”
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Application and Product-Volume-Specific Customization of BEOL Metal Pitch by Pagliarini, Samuel N., Isgenc, Mehmet Meric, Martins, Mayler G. A., Pileggi, Lawrence

“…High-volume manufacturing of integrated circuits is what drives the semiconductor industry and the scaling of CMOS; however, shrinking all feature sizes is not…”
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Logic IP for Low-Cost IC Design in Advanced CMOS Nodes by Isgenc, Mehmet Meric, Martins, Mayler G. A., Zackriya, V. Mohammed, Pagliarini, Samuel N., Pileggi, Larry

“…Routing closure and design-for-manufacturability (DFM) challenges exacerbate nonrecurring engineering (NRE) costs, a steep barrier to entry for advanced…”
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Single event transient mitigation through pulse quenching: Effectiveness at circuit level by Pagliarini, Samuel N., De B Naviner, Lirida A., Naviner, Jean-Francois

“…This paper exploits the pulse quenching effect in order to reduce circuit error rates due to single event transients in combinational logic. Although the…”
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Reliability assessment of combinational logic using first-order-only fanout reconvergence analysis by Pagliarini, Samuel N., Ban, Tian, Naviner, Lirida A. de B., Naviner, Jean-Francois

“…This paper proposes two heuristic-based approaches for assessing the reliability of combinational logic in digital circuits. Both approaches take into account…”
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A placement strategy for reducing the effects of multiple faults in digital circuits by Pagliarini, Samuel N., Pradhan, Dhiraj

“…This paper proposes a fault-aware placement strategy for digital circuits. Placement algorithms usually have a goal of reducing the overall chip area and…”
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Selective hardening methodology for combinational logic by Pagliarini, Samuel N., Naviner, Lirida A. de B., Naviner, Jean-Francois

“…Defects as well as soft errors are a growing concern in micro and nanoelectronics. Multiple faults induced by single event effects are expected to be seen more…”
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A hybrid reliability assessment method and its support of sequential logic modelling by Pagliarini, Samuel N., de B Naviner, Lirida A., Naviner, Jean-Francois, Pradhan, Dhiraj

“…This paper proposes a modified hybrid method for the reliability assessment of digital circuits. Such method deals naturally with the occurrence of multiple…”
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Selective hardening against multiple faults employing a net-based reliability analysis by Pagliarini, Samuel N., Naviner, Lirida A. de B., Naviner, Jean-Francois

“…This paper proposes a methodology for selective hardening combinational cells in digital circuits. Such analysis is performed by taking into account multiple…”
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Automatic selective hardening against soft errors: A cost-based and regularity-aware approach by Pagliarini, S. N., Ben Dhia, Arwa, de B Naviner, L. A., Naviner, J-F

“…This paper proposes a methodology to automatically apply selective hardening into a circuit based on the net hardening concept. Analysis is performed in the…”
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