Search Results - "PALIOURAS, V"

Reconfigurable RO-Path Delay Sensor by Sakellariou, P., Paliouras, V.

“…In this brief, we propose a method of analyzing signal propagation delay in certain digital circuits and a delay-sensing architecture. Based on controllability…”
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Simplified Hardware Implementation of Memoryless Dot Product for Neural Network Inference by Kouretas, I., Paliouras, V.

“…In this paper a simplified hardware implementation of a dot product arithmetic operation with constant coefficients is presented. The proposed methodology…”
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Improving Residue-Level Sparsity in RNS-based Neural Network Hardware Accelerators via Regularization by Kavvousanos, E., Sakellariou, V., Kouretas, I., Paliouras, V., Stouraitis, T.

“…Residue Number System (RNS) has recently attracted interest for the hardware implementation of inference in machine-learning systems as it provides promising…”
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A Low-Complexity High-Radix RNS Multiplier by Kouretas, I., Paliouras, V.

“…A graph-based technique is introduced for the design of a class of residue arithmetic multipliers, as well as a family of new high-radix digit adders. A…”
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A Low-Latency Syndrome-based Deep Learning Decoder Architecture and its FPGA Implementation by Kavvousanos, E., Paliouras, V.

“…Recently, Machine Learning has been considered as an alternative design paradigm for various communications sub-systems. However, the works that have assessed…”
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Optimizing Deep Learning Decoders for FPGA Implementation by Kavvousanos, E., Paliouras, V.

“…Recently, Deep Learning (DL) methods have been proposed for use in the decoding of linear block codes. While novel DL decoders show promising error correcting…”
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An Iterative Approach to Syndrome-based Deep Learning Decoding by Kavvousanos, E., Paliouras, V.

“…Recently, Machine Learning has been considered for use in various communications subsystems, providing an alternative paradigm for addressing core problems in…”
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Hardware Aspects of Parallel Neural Network Implementation by Kouretas, I., Paliouras, V.

“…In this paper a parallel neural network architecture is proposed targeting efficient hardware implementation on low-resource devices. Following the…”
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Residue arithmetic bases for reducing delay variation by Kouretas, I, Paliouras, V

“…In this paper the utilization of Residue Number System (RNS) is investigated as a tool for variation-tolerant design. In particular circuits using various RNS…”
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Hardware Implementation Aspects of a Syndrome-based Neural Network Decoder for BCH Codes by Kavvousanos, E., Paliouras, V.

“…Deep-Learning-based Decoders have been recently introduced for use with short-length codes. They have been found to act as a Soft-Decision-Decoding method…”
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Considering the alternatives in low-power design by Stouraitis, T., Paliouras, V.

“…The authors discuss employing alternative number systems to reduce power dissipation in portable devices and high-performance systems. They focus on two…”
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A novel architecture and a systematic graph-based optimization methodology for modulo multiplication by Dimitrakopoulos, G., Paliouras, V.

“…A novel hardware algorithm, a VLSI architecture, and an optimization methodology for residue multipliers are introduced in this paper. The proposed design…”
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Low-power logarithmic number system addition/subtraction and their impact on digital filters by Kouretas, I., Basetas, Ch, Paliouras, V.

“…This paper discusses techniques for low-power addition/ subtraction in the Logarithmic Number System (LNS) and evaluates their impact on digital filter…”
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A floating-point processor for fast and accurate sine/cosine evaluation by Paliouras, V., Karagianni, K., Stouraitis, T.

“…A VLSI architecture for fast and accurate floating-point sine/cosine evaluation is presented, combining floating-point and simple fixed-point arithmetic. The…”
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Simplified Hardware Implementation of the Softmax Activation Function by Kouretas, I., Paliouras, V.

“…In this paper a simplified hardware implementation of a CNN softmax layer is proposed. Initially the softmax activation function is analyzed in terms of…”
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Operation-saving VLSI architectures for 3D geometrical transformations by Karagianni, K., Paliouras, V., Diamantakos, G., Stouraitis, T.

“…Two VLSI architectures for the computationally efficient implementation of the elementary 3D geometrical transformations are introduced. The first one is based…”
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Delay-variation-tolerant FIR filter architectures based on the Residue Number System by Kouretas, I., Paliouras, V.

“…This paper investigates the use of the Residue Number System (RNS) in the hardware design of VLSI FIR filters implemented in nano-scale technologies prone to…”
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RNS multi-voltage low-power multiply-add unit by Kouretas, I, Paliouras, V

“…In this paper an efficient way to exploit multi-Vdd standard-cell libraries is quantitatively investigated as a means to reduce power consumption of…”
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A flexible high-throughput hardware architecture for a gaussian noise generator by Paraskevakos, I., Paliouras, V.

“…In this paper a flexible, high-throughput, low-complexity additive white gaussian noise (AWGN) channel generator is presented. The proposed generator employs a…”
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Residue arithmetic for designing multiply-add units in the presence of non-gaussian variation by Kouretas, I., Paliouras, V.

“…In this paper the utilization of Residue Number System (RNS) is investigated as a tool for variation-tolerant design. In particular circuits using various RNS…”
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