Search Results - "Oyeniran, Stephen Adeboye"
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1
High-Level Combined Deterministic and Pseudoexhuastive Test Generation for RISC Processors
Published 08-08-2019“…Recent safety standards set stringent requirements for the target fault coverage in embedded microprocessors, with the objective to guarantee robustness and…”
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Journal Article -
2
Mixed-level identification of fault redundancy in microprocessors
Published 29-07-2019“…2019 IEEE Latin American Test Symposium (LATS), Santiago, Chile, 2019, pp. 1-6 A new high-level implementation independent functional fault model for control…”
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Journal Article -
3
High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors
Published in Journal of electronic testing (01-02-2020)“…The paper proposes a novel high-level approach for implementation-independent generation of functional software-based self test programs for processors with…”
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Journal Article -
4
Parallel Pseudo-Exhaustive Testing of Array Multipliers with Data-Controlled Segmentation
Published in 2018 IEEE International Symposium on Circuits and Systems (ISCAS) (27-05-2018)“…This paper presents a new method for pseudo-exhaustive testing of standard array multipliers using a novel approach of data-controlled segmentation of the…”
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Conference Proceeding -
5
High-Level Functional Test Generation for Microprocessor Modules
Published in 2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems" (01-06-2019)“…A new high-level implementation-independent and automated test program generation method for RISC processors is proposed. For testing the control parts of the…”
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Conference Proceeding -
6
High-Level Fault Diagnosis in RISC Processors with Implementation-Independent Functional Test
Published in 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (01-07-2022)“…We propose a novel functional approach for Software-Based Self-Test generation and fault diagnosis for RISC processors in the case when low-level…”
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Conference Proceeding -
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Environment for Innovative University Research Training in the Field of Digital Test
Published in 2021 30th Annual Conference of the European Association for Education in Electrical and Information Engineering (EAEEIE) (01-09-2021)“…In this paper we target three methods and goals for teaching research, called active learning, authentic learning by doing and reflexing learning. We discuss…”
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Conference Proceeding -
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Implementation-Independent Test Generation for a Large Class of Faults in RISC Processor Modules
Published in 2021 24th Euromicro Conference on Digital System Design (DSD) (01-09-2021)“…In this paper, a concept for generating tests for RISC processors is proposed relying solely on functional information such as the instruction set without any…”
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Conference Proceeding -
9
Implementation-Independent Functional Test for Transition Delay Faults in Microprocessors
Published in 2020 23rd Euromicro Conference on Digital System Design (DSD) (01-08-2020)“…We propose a method for synthesis of Software-Based Self-Test (SBST) for testing RISC type of microprocessors without needing the knowledge of implementation…”
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Conference Proceeding -
10
Minimization of the High-Level Fault Model for Microprocessor Control Parts
Published in 2018 16th Biennial Baltic Electronics Conference (BEC) (01-10-2018)“…The paper presents a method for representing the instruction set truth tables of microprocessors with High-Level Decision Diagrams (HLDD). A behavior level…”
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Conference Proceeding -
11
Multiple control fault testing in digital systems with high-level decision diagrams
Published in 2016 IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR) (01-05-2016)“…A new method of high-level test generation for control faults in digital systems is proposed. High-level faults of any multiplicity are assumed to be present,…”
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Conference Proceeding -
12
Combined pseudo-exhaustive and deterministic testing of array multipliers
Published in 2018 IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR) (01-05-2018)“…The paper presents a new method for bit-parallel testing of array multipliers using a novel approach of data-controlled segmentation of the circuit to…”
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Conference Proceeding -
13
Teaching Digital System Test
Published in 2017 27th EAEEIE Annual Conference (EAEEIE) (01-06-2017)“…The paper proposes a novel concept of teaching how to test complex digital systems. A set of methods and tools is presented to support laboratory scenarios for…”
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Conference Proceeding -
14
High-level test generation for processing elements in many-core systems
Published in 2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) (01-07-2017)“…The advent of many-core system-on-chips (SoC) will involve new scalable hardware/software mechanisms that can efficiently utilize the abundance of…”
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Conference Proceeding -
15
High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors
Published in 2019 IEEE European Test Symposium (ETS) (01-05-2019)“…Recent safety standards set stringent requirements for the target fault coverage in embedded microprocessors, with the objective to guarantee robustness and…”
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Conference Proceeding -
16
Implementation-Independent Functional Test Generation for RISC Microprocessors
Published in 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC) (01-10-2019)“…We propose a generic strategy for formalized synthesis of Software-Based Self-Test (SBST) for testing microprocessors with RISC architecture with the goal to…”
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Conference Proceeding -
17
Mixed-level identification of fault redundancy in microprocessors
Published in 2019 IEEE Latin American Test Symposium (LATS) (01-03-2019)“…A new high-level implementation independent functional fault model for control faults in microprocessors is introduced. The fault model is based on the…”
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Conference Proceeding -
18
Application Specific True Critical Paths Identification in Sequential Circuits
Published in 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS) (01-07-2019)“…The extreme complexity of digital systems enabled by nanometer-scale implementation technologies comes along with strengthened design requirements that are…”
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Conference Proceeding -
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High-level test data generation for software-based self-test in microprocessors
Published in 2017 6th Mediterranean Conference on Embedded Computing (MECO) (01-06-2017)“…A new high-level fault model and test generation method for software-based self-test in microprocessors (MP) is proposed and investigated. The model is derived…”
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Conference Proceeding -
20
From online fault detection to fault management in Network-on-Chips: A ground-up approach
Published in 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) (01-04-2017)“…Due to the ongoing miniaturization of silicon technology beyond the sub-micron domain and the trend of integrating ever more components on a single chip, the…”
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Conference Proceeding