Search Results - "Otfinowski, P."

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  1. 1

    SPHIRD -Single Photon Counting Pixel Readout ASIC with Pulse Pile-up Compensation Methods by Grybos, P., Kleczek, R., Kmon, P., Otfinowski, P., Fajardo, P., Magalhaes, D., Ruat, M.

    “…This paper presents the design and measurement results of a prototype SPHIRD-1 ASIC in the CMOS 40 nm process. The chip is dedicated to high count rate single…”
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    Journal Article
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    Time and energy measuring front-end electronics for long silicon strip detectors readout by Kleczek, R., Szczygiel, R., Grybos, P., Otfinowski, P., Kasinski, K.

    “…We report on the design of a self-triggered analog front-end readout electronics dedicated for signal detection from double-sided silicon microstrip sensors…”
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    Conference Proceeding
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    Hybrid Detector with Interpixel Communication for Color X-ray Imaging by Grybos, P., Kleczek, R., Kmon, P., Krzyzanowska, A., Otfinowski, P., Szczygiel, R., Zoladz, M.

    “…This paper presents a readout integrated circuit of pixel architecture called MPIX (Multithreshold PIXels), designed for CdTe pixel detectors used in…”
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    Conference Proceeding
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    Increasing the Position Resolution in Single Photon Counting Pixel Readout IC by Real-Time Interpixel Communications by Otfinowski, Piotr Krzysztof, Magalhaes, D., Fajardo, P., Grybos, P., Kleczek, R., Kmon, P., Ruat, M.

    “…This brief presents the design and measurement results of a prototype integrated circuit (IC) of pixel architecture operating in single photon counting mode…”
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    Journal Article
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    Offset correction system for 128-channel self-triggering readout chip with in-channel 5-bit energy measurement functionality by Otfinowski, P., Grybos, P., Szczygiel, R., Kasinski, K.

    “…We report on a novel, two-stage 8-bit trimming solution dedicated for multichannel systems with reduced trim DAC area occupancy. The presented design was used…”
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    Journal Article
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    Measurements of Matching and Noise Performance of a Prototype Readout Chip in 40 nm CMOS Process for Hybrid Pixel Detectors by Maj, P., Grybos, P., Szczygiel, R., Kmon, P., Kleczek, R., Drozd, A., Otfinowski, P., Deptuch, G.

    Published in IEEE transactions on nuclear science (01-02-2015)
    “…The paper presents a prototype integrated circuit built in a 40 nm CMOS process for readout of a hybrid pixel detector. The core of the IC constitutes a matrix…”
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    Journal Article
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    Design and measurements of low power multichannel chip for recording and stimulation of neural activity by Zoladz, M., Kmon, P., Grybos, P., Szczygiel, R., Kleczek, R., Otfinowski, P., Rauza, J.

    “…A 64-channel Neuro-Stimulation-Recording chip named NRS64 for neural activity measurements has been designed and tested. The NRS64 occupies 5×5 mm 2 of silicon…”
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    Conference Proceeding Journal Article
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    A bidirectional 64-channel neurochip for recording and stimulation neural network activity by Zoladz, M., Kmon, P., Grybos, P., Szczygiel, R., Kleczek, R., Otfinowski, P.

    “…We present the design and measurements of a novel 64 channel ASIC dedicated for recording and stimulation of neural network activity. Chip is designed in…”
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    Conference Proceeding
  12. 12

    A 2.5MS/s 225 µW 8-bit charge redistribution SAR ADC for multichannel applications by Otfinowski, P

    “…This paper presents a design of integrated analog-to-digital converter implemented in UMC CMOS 180nm technology dedicated to multichannel readout circuits. The…”
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    Conference Proceeding
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    Area efficient front-end readout electronics for pixel detector based on inverter amplifier by Kleczek, R., Otfinowski, P., Grybos, P.

    “…Modern X-ray imaging applications require low noise and power, high rate readout front-end electronics. A widely used, dedicated for semiconductor detectors…”
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    Conference Proceeding
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    The design of low power low noise high speed CMOS readout front-end electronics for silicon strip detectors by Kleczek, R., Grybos, P., Otfinowski, P.

    “…This paper presents a design of low power and low noise, high speed analog readout front-end electronic system implemented in CMOS 180 nm UMC technology for…”
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    Conference Proceeding
  16. 16

    A 10-bit 3MS/s low-power charge redistribution ADC in 180nm CMOS for neural application by Otfinowski, P., Grybos, P., Kleczek, R.

    “…This paper presents a design of low-power charge redistribution ADC implemented in UMC 180nm CMOS. The described circuit is dedicated to a neurobiological…”
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    Conference Proceeding
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    Integrated circuit for wireless inductive powering implemented in 180nm CMOS process by Zoladz, M., Kmon, P., Otfinowski, P., Rauza, J., Grybos, P.

    “…Our report is on the simulation results and the design of the integrated circuit dedicated for inductive powering of a neural recording system on a chip. Four…”
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    Conference Proceeding
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    Integrated control unit for wireless recording of brain activity by Soladz, M., Szczygiel, R., Otfinowski, P., Grybos, P.

    “…Multichannel integrated recording systems are the gate for our understanding of mammalian brain activity. For in vivo neurobiological brain experiment on…”
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    Conference Proceeding