Search Results - "Osburn, C M"

Impact of gate workfunction on device performance at the 50 nm technology node by De, Indranil, Johri, Deepak, Srivastava, Anadi, Osburn, C.M.

“…The optimal gate electrode workfunction was determined for the 50 nm technology node using a simulation strategy that takes into account the impact of…”
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Low parasitic resistance contacts for scaled ULSI devices by OSBURN, C. M, BELLUR, K. R

“…Unless contact resistivity is reduced, the contact resistance ultimately becomes higher than the channel resistance and becomes useless in modern day devices…”
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Formation of silicided, ultra-shallow junctions using low thermal budget processing by OSBURN, C. M

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Metal Silicides: Active elements of ULSI contacts by Osburn, C M, Tsai, J Y, Sun, J

“…As device dimensions scale to the 0.1 µm regime, the self-aligned silicide (SALICIDE) contact technology increasingly becomes an integral part of both the…”
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Defect annihilation in shallow p+ junctions using titanium silicide by WEN, D. S, SMITH, P. L, OSBURN, C. M, ROZGONYI, G. A

“…The residual extended defects due to end-of-range ion implantation damage can be totally eliminated by Ti silicidation. Shallow p+ junctions were formed by…”
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Improved stability of thin cobalt disilicide films using BF2 implantation by WANG, Q. F, TSAI, J. Y, OSBURN, C. M, CHAPMAN, R, MCGUIRE, G. E

“…The thermal stability of ∼50 nm CoSi2 and TiSi2 thin films after BF2+ implantation was investigated. The electrical characteristics of silicide films were…”
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Ultra-shallow junction formation using silicide as a diffusion source and low thermal budget by Wang, Q., Osburn, C.M., Canovai, C.A.

“…Ultra-shallow p/sup +//n and n/sup +//p junctions were fabricated using SADS (silicide-as-diffusion-source) and ITS (ion-implantation-through-silicide…”
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Analysis of the effects of scaling on interconnect delay in ULSI circuits by Bothra, S., Rogers, B., Kellam, M., Osburn, C.M.

“…A model has been developed to assess interconnect delay in ULSI circuits as dimensions are scaled deep into the submicrometer regime. In addition to RC delay,…”
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Optimization of the germanium preamorphization conditions for shallow-junction formation by Ozturk, M.C., Wortman, J.J., Osburn, C.M., Ajmera, A., Rozgonyi, G.A., Frey, E., Chu, W.-K., Lee, C.

“…Shallow p/sup +/-n and n/sup +/-p junctions were formed in germanium preamorphized Si substrates. Germanium implantation was carried out over the energy range…”
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Effects of silicon layer properties on device reliability for 0.1-μm SOI n-MOSFET design strategies by Hulfachor, R.B., Kim, K.W., Littlejohn, M.A., Osburn, C.M.

“…We employ an advanced simulation method to investigate the effects of silicon layer properties on hot-electron-induced reliability for two 0.1- mu m SOI…”
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Effects of ion implantation on deep-submicrometer, drain-engineered MOSFET technologies by Stinson, M.G., Osburn, C.M.

“…The effects of ion implantation on the reliability of thin-oxide (7-nm) MOS structures using drain engineering, e.g. lightly doped-drain (LDD), Inverse-T,…”
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Thin‐oxide degradation along feature edges during reactive ion etching of polysilicon gates by Markus, K., Osburn, C. M., Magill, P., Bobbio, S. M.

“…Enhanced leakage current through the gate oxide insulator and degraded oxide breakdown voltages were observed following hexode reactive ion etching and…”
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Impact of super-steep-retrograde channel doping profiles on the performance of scaled devices by De, I., Osburn, C.M.

“…Super-steep retrograded (SSR) channels were compared to uniformly doped (UD) channels as devices are scaled down from 250 nm to the 50 nm technology node,…”
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Tunneling leakage in Ge preamorphized shallow junctions by Wen, D.-S., Goodwin-Johansson, S.H., Osburn, C.M.

“…CMOS shallow junctions with depths less than 0.2 mu m were fabricated using Ge preamorphization and rapid thermal annealing. A low bulk generation current (<1…”
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Quantitative secondary ion mass spectrometry depth profiling of TiSi2 films by Corcoran, S. F., Osburn, C. M., Parikh, N., Linton, R. W., Griffis, D. P.

“…This paper reports on an analytical method for the quantitative depth profiling of multilayer samples by secondary ion mass spectrometry (SIMS). This method is…”
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Design and integration considerations for end-of-the roadmap ultrashallow junctions by Osburn, C. M., De, I., Yee, K. F., Srivastava, A.

“…Device simulations and response surface analysis have been used to quantify the trade-offs and issues encountered in designing ultrashallow junctions for the…”
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Effect of electron trapping on IGFET characteristics by Ning, T. H., Osburn, C. M., Yu, H. N.

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Electron trapping at positively charged centers in SiO2 by Ning, T. H., Osburn, C. M., Yu, H. N.

“…Evidence is presented which indicates that positive oxide charge centers in thin films of thermally grown silicon dioxide are electron traps with an average…”
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Impact of epi facets on deep submicron elevated source/drain MOSFET characteristics by Sun, J.J., Osburn, C.M.

“…Deep submicron elevated source/drain (S/D) MOSFET's with epi facets, without facets, and with a second sidewall spacer covering the facets were studied using…”
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Reliability of in-situ rapid thermal gate dielectrics in deep submicrometer MOSFET's by Zhang, K.X., Osburn, C.M.

“…Several in-situ, rapid thermal gate dielectrics, 6.5-nm thick, including RTO, RTCVD, and RPECVD were used to fabricate fully implanted 0.25-/spl mu/m NMOSFET's…”
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