Search Results - "Orailoglu, A."

Test volume and application time reduction through scan chain concealment by Bayraktaroglu, Ismet, Orailoglu, Alex

“…A test pattern compression scheme is proposed in order to reduce test data volume and application time. The number of scan chains that can be supported by an…”
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Architectures for silicon nanoelectronics and beyond by Bahar, R.I., Lau, C., Hammerstrom, D., Marculescu, D., Harlow, J., Orailoglu, A., Joyner, W.H., Pedram, M.

“…Although nanoelectronics won't replace CMOS for some time, research is needed now to develop the architectures, methods, and tools to maximally leverage…”
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Low-Power Scan Testing for Test Data Compression Using a Routing-Driven Scan Architecture by Dong Xiang, Dianwei Hu, Qiang Xu, Orailoglu, A.

“…A new scan architecture is proposed to reduce peak test power and capture power. Only a subset of scan flip-flops is activated to shift test data or capture…”
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Low-power instruction bus encoding for embedded processors by Petrov, P., Orailoglu, A.

“…This paper presents a low-power encoding framework for embedded processor instruction buses. The encoder is capable of adjusting its encoding not only to suit…”
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Tag compression for low power in dynamically customizable embedded processors by Petrov, P., Orailoglu, A.

“…We present a methodology for power reduction by instruction/data cache-tag compression for low-power embedded processors. By statically analyzing the code/data…”
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Concurrent application of compaction and compression for test time and data volume reduction in scan designs by Bayraktaroglu, I., Orailoglu, A.

“…A test pattern compression scheme for test data volume and application time reduction is proposed. While compression reduces test data volume, the increased…”
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Reducing test application time through test data mutation encoding by Reda, S., Orailoglu, A.

“…In this paper we propose a new compression algorithm geared to reduce the time needed to test scan-based designs. Our scheme compresses the test vector set by…”
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Towards a cost-effective hardware trojan detection methodology by Paseman, R., Orailoglu, A.

“…Due to the increasing globalization of integrated circuit fabrication, hardware security has emerged as a major issue, necessitating hardware trojan detection…”
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Decompression hardware determination for test volume and time reduction through unified test pattern compaction and compression by Bayraktaroglu, I., Orailoglu, A.

“…A methodology for the determination of decompression hardware that guarantees complete fault coverage for a unified compaction/compression scheme is proposed…”
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The construction of optimal deterministic partitionings in scan-based BIST fault diagnosis: mathematical foundations and cost-effective implementations by Bayraktaroglu, I., Orailoglu, A.

“…Partitioning techniques enable identification of fault-embedding scan cells in scan-based BIST. We introduce deterministic partitioning techniques capable of…”
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Test power reductions through computationally efficient, decoupled scan chain modifications by Sinanoglu, O., Orailoglu, A.

“…SOC test time minimization hinges on the attainment of core test parallelism; yet test power constraints hamper this parallelism as excessive power dissipation…”
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Transforming binary code for low-power embedded processors by Petrov, P., Orailoglu, A.

“…Two program code transformation methodologies reduce the power consumption of instruction communication buses in embedded processors. Aimed at deep-submicron…”
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Circularscan: a scan architecture for test cost reduction by Arslan, B., Orailoglu, A.

“…Scan-based designs are widely used to decrease the complexity of the test generation process; nonetheless, they increase test time and volume. A new scan…”
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Performance and power effectiveness in embedded processors - customizable partitioned caches by Petrov, P., Orailoglu, A.

“…This paper explores an application-specific customization technique for the data cache, one of the foremost area/power consuming and performance determining…”
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Enhancing reliability of RTL controller-datapath circuits via Invariant-based concurrent test by Makris, Y., Bayraktaroglu, I., Orailoglu, A.

“…We present a low-cost concurrent test methodology for enhancing the reliability of RTL controller-datapath circuits, based on the notion of path invariance…”
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Design of concurrent test Hardware for Linear analog circuits with constrained hardware overhead by Ozev, S., Orailoglu, A.

“…Concurrent detection of failures in analog circuits is becoming increasingly more important as safety-critical systems become more widespread. A methodology…”
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Test power reduction through minimization of scan chain transitions by Sinanoglu, O., Bayraktaroglu, I., Orailoglu, A.

“…Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power…”
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Test application time and volume compression through seed overlapping by Rao, Wenjing, Bayraktaroglu, Ismet, Orailoglu, Alex

“…We propose in this paper an extension on the Scan Chain Concealment technique to further reduce test time and volume requirement. The proposed methodology…”
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Efficient construction of aliasing-free compaction circuitry by Sinanoglu, O., Orailoglu, A.

“…Parallel testing of cores can reduce SOC test times, but the finite number of chip I/Os limits such parallelism. Space and time compaction can maximize the…”
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Concurrent test for digital linear systems by Bayraktaroglu, I., Orailoglu, A.

“…Invariant-based concurrent test schemes can provide economical solutions to the problem of concurrent error detection. An invariant-based concurrent…”
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