Search Results - "Oowaki, Y"

Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems by Chen Kong Teh, Hamada, M., Fujita, T., Hara, H., Ikumi, N., Oowaki, Y.

“…This paper introduces a new family of low-power and high-performance flip-flops, namely conditional data mapping flip-flops (CDMFFs), which reduce their…”
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A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling by Fujiyoshi, T., Shiratake, S., Nomura, S., Nishikawa, T., Kitasho, Y., Arakida, H., Okuda, Y., Tsuboi, Y., Hamada, M., Hara, H., Fujita, T., Hatori, F., Shimazawa, T., Yahagi, K., Takeda, H., Murakata, M., Minami, F., Kawabe, N., Kitahara, T., Seta, K., Takahashi, M., Oowaki, Y., Furuyama, T.

“…A single-chip H.264 and MPEG-4 audio-visual LSI for mobile applications including terrestrial digital broadcasting system (ISDB-T / DVB-H) with a module-wise,…”
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A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive by Takashima, D., Shuto, S., Kunishima, I., Takenaka, H., Oowaki, Y., Tanaka, S.

“…A nonvolatile chain FRAM adopting a new cell-plate-line drive technique was demonstrated. Two key circuit techniques, a two-way metal cell-plate line and a…”
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Sub-0.1 mu m circuit design with substrate-over-biasing by Oowaki, Y, Noguchi, M, Takagi, S, Takashima, D, Ono, M, Matsunaga, Y, Sunouchi, K, Kawaguchiya, H, Matsuda, S, Kamoshida, M, Fuse, T, Watanabe, S, Toriumi, A, Manabe, S, Hojo, A

“…To realize substrate-over-biasing and gate-substrate tie in one chip, the key device structure is shallow well laterally isolated by trench isolation and…”
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Back gate effects on threshold voltage sensitivity to SOI thickness in fully-depleted SOI MOSFETs by Noguchi, M., Numata, T., Mitani, Y., Shino, T., Kawanaka, S., Oowaki, Y., Toriumi, A.

“…The dependence of threshold voltage on silicon-on-insulator (SOI) thickness is studied on fully-depleted SOI MOSFETs, and, for this purpose, back-gate oxide…”
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A novel circuit technology with surrounding gate transistors (SGT's) for ultra high density DRAM's by Watanabe, S., Tsuchida, K., Takashima, D., Oowaki, Y., Nitayama, A., Hieda, K., Takato, H., Sunouchi, K., Horiguchi, F., Ohuchi, K., Masuoka, F., Hara, H.

“…This paper describes a novel circuit technology with Surrounding Gate Transistors (SGT's) For ultra high density DRAM's. In order to reduce the chip size…”
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A novel power-off mode for a battery-backup DRAM by Takashima, D., Oowaki, Y.

“…This paper proposes a new DRAM power-off mode, in which the power source is completely shut off during the standby cycle, resulting in a zero standby leakage…”
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Noise suppression scheme for gigabit-scale and gigabyte/s data-rate LSI's by Takashima, D., Oowaki, Y., Watanabe, S., Ohuchi, K.

“…In order to reduce the power/ground noise due to the off-chip parasitic inductance and realize gigabit-scale and ultra-high bandwidth large scale integrations…”
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A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI by Hamada, M., Hara, H., Fujita, T., Chen Kong Teh, Shimazawa, T., Kawabe, N., Kitahara, T., Kikuchi, Y., Nishikawa, T., Takahashi, M., Oowaki, Y.

“…A novel conditional clocking flip-flop is proposed. The flip-flop circuit does not consume any power when the data input of the flip-flop does not change its…”
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Standby/active mode logic for sub-1-V operating ULSI memory by Takashima, D., Watanabe, S., Nakano, H., Oowaki, Y., Ohuchi, K., Tango, H.

“…New gate logics, standby/active mode logic I and II, for future 1 Gb/4 Gb DRAMs and battery operated memories are proposed. The circuits realize sub-l-V supply…”
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An experimental DRAM with a NAND-structured cell by Hasegawa, T., Takashima, D., Ogiwara, R., Ohta, M., Shiratake, S.-I., Hamamoto, T., Yamada, T., Aoki, M., Ishibashi, S., Oowaki, Y., Watanabe, S., Masuoka, F.

“…An experimental 256-Mb dynamic random access memory using a NAND-structured cell (NAND DRAM) has been fabricated. The NAND-structured cell has four memory…”
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A 33-ns 64-Mb DRAM by Oowaki, Y., Tsuchida, K., Watanabe, Y., Takashima, D., Ohta, M., Nakano, H., Watanabe, S., Nitayama, A., Horiguchi, F., Ohuchi, K., Masuoka, F.

“…A 64-Mb CMOS dynamic RAM (DRAM) measuring 176.4 mm/sup 2/ has been fabricated using a 0.4- mu m N-substrate triple-well CMOS, double-poly, double-polycide,…”
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Word-line architecture for highly reliable 64-Mb DRAM by Takashima, D., Oowaki, Y., Ogiwara, R., Watanabe, Y., Tsuchida, K., Ohta, M., Nakano, H., Watanabe, S., Ohuchi, K.

“…A unique word-line voltage control method for the 64-Mb DRAM and beyond is proposed. It realizes a constant lifetime for a thin gate oxide. This method…”
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A 10.4pJ/b (32, 8) LDPC decoder with time-domain analog and digital mixed-signal processing by Miyashita, D., Yamaki, R., Hashiyoshi, K., Kobayashi, H., Kousai, S., Oowaki, Y., Unekawa, Y.

“…Analog computation is potentially more efficient in certain arithmetic operations since a single wire can represent multiple bits of information, while digital…”
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Open/folded bit-line arrangement for ultra-high-density DRAM's by Takashima, D., Watanabe, S., Nakano, H., Oowaki, Y., Ohuchi, K.

“…An open/folded bit-line (BL) arrangement for scaled DRAM's is proposed. This BL arrangement offers small die size and good array noise immunity. In this…”
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New nibbled-page architecture for high-density DRAMs by Numata, K., Oowaki, Y., Itoh, Y., Hara, T., Tsuchida, K., Ohta, M., Watanabe, S., Ohuchi, K.

“…A nibbled-page architecture which can be used to access all column addresses on the selected row address randomly in units of 8 bits at the 100 Mbit/s data…”
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The stabilized reference-line (SRL) technique for scaled DRAMs by Tsuchida, K., Oowaki, Y., Ohta, M., Takashima, D., Watanabe, S., Ohuchi, K., Masuoka, F.

“…The stabilized reference-line (SRL) technique, which reduces bit-line interference noise, is described. This technique can eliminate the capacitance coupling…”
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VIB-1 new hot-carrier-induced degradation phenomena in half-micrometer MOS transistors by Nitayama, A., Takenouchi, N., Hamamoto, T., Oowaki, Y.

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Session 2 overview - non-volatile memory by Sofer, Y., Oowaki, Y.

“…Consumer-electronic applications such as cellular phones and digital cameras are driving a need for higher-performance and lower-cost-memory solutions. This…”
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An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode by Watanabe, S., Oowaki, Y., Itoh, Y., Sakui, K., Numata, K., Fuse, T., Kobayashi, T., Tsuchida, K., Chiba, M., Hara, T., Ohta, M., Horiguchi, F., Hieda, K., Mitayama, A., Hamamoto, T., Ohuchi, K., Masuoka, F.

“…A 5-V 4M-word*4-b dynamic RAM (random-access memory) with a 100-MHz serial read/write mode using 0.7- mu m triple-tub CMOS technology is discussed. The RAM…”
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