Search Results - "Onai, Takahiro"

Silicon light-emitting transistor for on-chip optical interconnection by Saito, Shin-ichi, Hisamoto, Digh, Shimizu, Haruka, Hamamura, Hirotaka, Tsuchiya, Ryuta, Matsui, Yuichi, Mine, Toshiyuki, Arai, Tadashi, Sugii, Nobuyuki, Torii, Kazuyoshi, Kimura, Shin'ichiro, Onai, Takahiro

“…The authors propose a light-emitting field-effect transistor with the active layer made of the ultrathin single crystal silicon with the (100) surface…”
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Improved theory for remote-charge-scattering-limited mobility in metal–oxide–semiconductor transistors by Saito, Shin-ichi, Torii, Kazuyoshi, Hiratani, Masahiko, Onai, Takahiro

“…Transport theory is extended to include the remote-charge-scattering-limited electron mobility of metal–oxide–semiconductor field-effect transistors. We…”
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Electro-Luminescence from Ultra-Thin Silicon by Saito, Shin-ichi, Hisamoto, Digh, Shimizu, Haruka, Hamamura, Hirotaka, Tsuchiya, Ryuta, Matsui, Yuichi, Mine, Toshiyuki, Arai, Tadashi, Sugii, Nobuyuki, Torii, Kazuyoshi, Kimura, Shin'ichiro, Onai, Takahiro

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Synthesis, Monolayer Formation, and Control of Electrical Characteristics of 3-nm-Diameter Gold Nanoparticles by Arai, Tadashi, Saito, Shin-ichi, Fukuda, Hiroshi, Onai, Takahiro

“…A two-dimensional (2D) artificial lattice composed of metal nanoparticles was fabricated and its electrical characteristics were controlled. Each nanoparticle…”
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Analytical quantum mechanical model for accumulation capacitance of MOS structures by Saito, S., Torii, K., Hiratani, M., Onai, T.

“…We propose a new analytical model to quantitatively simulate capacitance-voltage (C-V) characteristics under accumulation conditions in…”
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Effects of remote-surface-roughness scattering on carrier mobility in field-effect-transistors with ultrathin gate dielectrics by Saito, Shin-ichi, Torii, Kazuyoshi, Shimamoto, Yasuhiro, Tsujikawa, Shimpei, Hamamura, Hirotaka, Tonomura, Osamu, Mine, Toshiyuki, Hisamoto, Digh, Onai, Takahiro, Yugami, Jiro, Hiratani, Masahiko, Kimura, Shin’ichiro

“…We examined effects of the remote surface roughness, which is the roughness between the polycrystalline silicon gate and gate dielectric, on the inversion…”
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Effect of interfacial oxide on electron mobility in metal insulator semiconductor field effect transistors with Al2O3 gate dielectrics by TORII, Kazuyoshi, SHIMAMOTO, Yasuhiro, SAITO, Shin-Ichi, OBATA, Katsunori, YAMAUCHI, Tsuyoshi, HISAMOTO, Digh, ONAI, Takahiro, HIRATANI, Masahiko

“…We investigated the transistor properties and electron mobility of n-field-effect transistors with Al2O3 gate dielectrics. Post-deposition annealing was…”
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Negative bias temperature instability of pMOSFETs with ultra-thin SiON gate dielectrics by Tsujikawa, S., Mine, T., Watanabe, K., Shimamoto, Y., Tsuchiya, R., Ohnishi, K., Onai, T., Yugami, J., Kimura, S.

“…The negative bias temperature instability (NBTI) of pMOSFETs with ultra-thin gate dielectrics was investigated from four points of view: basic mechanism of…”
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Effect of interfacial oxide on electron mobility in metal insulator semiconductor field effect transistors with Al 2O 3 gate dielectrics by Torii, Kazuyoshi, Shimamoto, Yasuhiro, Saito, Shin-ichi, Obata, Katsunori, Yamauchi, Tsuyoshi, Hisamoto, Digh, Onai, Takahiro, Hiratani, Masahiko

“…We investigated the transistor properties and electron mobility of n-field-effect transistors with Al 2O 3 gate dielectrics. Post-deposition annealing was…”
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Ultra-low-power and high-speed SiGe base bipolar transistors for wireless telecommunication systems by Kondo, M., Oda, K., Ohue, E., Shimamoto, H., Tanabe, M., Onai, T., Washio, K.

“…Ultra-low-power and high-speed SiGe base bipolar transistors that can be used in RF sections of multi-GHz telecommunication systems have been developed. The…”
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12-ps ECL using low-base-resistance Si bipolar transistor by self-aligned metal/IDP technology by Onai, T., Ohue, E., Tanabe, M., Washio, K.

“…A self-aligned metal/IDP (SMI) technology is proposed to reduce the external base resistance and to enable fabrication of high-speed bipolar transistors. This…”
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A selective-epitaxial-growth SiGe-base HBT with SMI electrodes featuring 9.3-ps ECL-gate delay by Washio, K., Ohue, E., Oda, K., Tanabe, M., Shimamoto, H., Onai, T., Kondo, M.

“…An ultra-high-speed selective-epitaxial-growth SiGe-base heterojunction bipolar transistor (HBT) with self-aligned stacked metal/in-situ doped poly-Si (IDP)…”
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Self-aligned metal/IDP Si bipolar technology with 12-ps ECL and 45-GHz dynamic frequency divider by Washio, K., Ohue, E., Tanabe, M., Onai, T.

“…Ultra-high-speed operation using a self-aligned stacked metal/in situ doped poly-Si (IDP) (referred to as SMI) Si bipolar transistor technology that offers low…”
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A very small bipolar transistor technology with sidewall polycide base electrode for ECL-CMOS LSIs by Shiba, T., Tamaki, Y., Onai, T., Kiyota, Y., Kure, T., Nakamura, T.

“…Very small, high-performance, silicon bipolar transistors (SPOTEC) are developed for use in ECL-CMOS LSIs. The transistors are fabricated with a sidewall…”
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Self-Aligned Metal/IDP Si Bipolar Technology with 12-ps ECL and 45-GHz Dynamic Frequency Divider by Washio, Katsuyoshi, Ohue, Eiji, Tanabe, Masamichi, Onai, Takahiro

“…A self-aligned stacked metal/IDP (SMI) Si bipolar transistor technology that offers low base resistance with shallow impurity profiles is described. This…”
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Ultra-thin-base Si bipolar transistor using rapid vapor-phase direct doping (RVD) by Kiyota, Y., Onai, T., Nakamura, T., Inada, T., Kuranouchi, A., Hirano, Y.

“…A novel doping method called rapid vapor-phase direct doping (RVD) is developed to form ultra-shallow junctions. The base region of a conventional bipolar…”
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SEPIA: a new isolation structure for soft-error-immune LSIs by Onai, T., Nakamura, T., Homma, N.

“…A new isolation structure for soft-error immunity has been developed. This structure, SEPIA (soft-error-preventing isolation by charge absorption), is suitable…”
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Self-aligned complementary bipolar technology for low-power dissipation and ultra-high-speed LSIs by Onai, T., Ohue, E., Idei, Y., Tanabe, M., Shimamoto, H., Washio, K., Nakamura, T.

“…Fully symmetrical complementary bipolar transistors for low power-dissipation and ultra-high-speed LSIs have been integrated in the same chip using a 0.3-/spl…”
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A high-current-gain low-temperature pseudo-heterojunction bipolar transistor utilizing sidewall base-contact structure (SICOS) by Yano, K., Nakazato, K., Miyamoto, M., Onai, T., Aoki, M., Shimohigashi, K.

“…An experimental pseudo-heterojunction bipolar transistor (HBT) is described. The pseudo-HBT is a homojunction bipolar transistor having a moderately doped…”
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Process design of a novel shielded SBD and its device characteristics by Sagara, K., Onai, T., Homma, N., Nakamura, T.

“…A shielded Schottky-barrier diode that has the shielding p-layer between the active n-layer and the n/sup +/-buried layer is described. To demonstrate the…”
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