Search Results - "Ohyu, Kiyonori"

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  1. 1

    Advantages of fluorine introduction in boron implanted shallow p+/n-junction formation by OHYU, K, ITOGA, T, NATSUAKI, N

    Published in Japanese Journal of Applied Physics (01-03-1990)
    “…The advantages of fluorine introduction on fabrication of shallow p + /n-junctions have been demonstrated. This was done by implanting fluorine onto the boron…”
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    Journal Article
  2. 2
  3. 3

    Recrystallization of silicon-on-insulator structures by sinusoidally-scanned electron beams by ISHIWARA, H, OHYU, K, HORITA, S, FURUKAWA, S

    Published in Japanese Journal of Applied Physics (01-02-1985)
    “…This paper describes the recrystallization by an electron beam of Si films deposited on SiO 2 /Si structures. To achieve pseudo-line-shaped heating, a spot…”
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    Journal Article
  4. 4

    Direct observation of worst-bit leakage currents of DRAM by Mori, Y., Kamohara, S., Moniwa, M., Ohyu, K., Yamanaka, T., Yamada, R.

    Published in IEEE transactions on electron devices (01-02-2006)
    “…We build a method for measuring leakage current of anomalously leaky cells (tail cells) in dynamic random access memories. We find that the traps in tail cells…”
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    Journal Article
  5. 5

    Improvement of Data Retention Time Property by Reducing Vacancy-Type Defect in DRAM Cell Transistor by Okonogi, K., Ohyu, K., Umeda, T., Miyake, H., Fujieda, S.

    “…As electric equipment for portable spreads through a world widely, development of a low power consumption device is required strongly. DRAM development also…”
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    Conference Proceeding
  6. 6

    A mechanism and a reduction technique for large reverse leakage current in p-n junctions by Ohyu, K., Ohkura, M., Hiraiwa, A., Watanabe, K.

    Published in IEEE transactions on electron devices (01-08-1995)
    “…The origin of anomalously large p-n junction leakage current in Si is investigated. The leakage has strong electric field dependence and weak temperature…”
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    Journal Article
  7. 7

    Hot-electron hardened Si-gate MOSFET utilizing F implantation by Nishioka, Y., Ohyu, K., Ohji, Y., Natuaki, N., Mukai, K., Ma, T.-P.

    Published in IEEE electron device letters (01-04-1989)
    “…A technique is presented for incorporating fluorine (F) into the gate-oxide film, and the subsequent improvement of channel-hot-electron hardness of the…”
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    Journal Article
  8. 8

    A new experimental method for evaluating electric field at the junctions of DRAM cell transistors and the effect of electric field strength on the retention characteristics of DRAM by Mori, Y., Takeda, Y., Kimura, S., Ohyu, K., Uchiyama, H., Yamada, R.

    “…A new method for the analysis of DRAM data retention characteristics is developed. We use a test element group (TEG) and detailed simulation to analyze the…”
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    Conference Proceeding
  9. 9

    Design and performance of 0.1- mu m CMOS devices using low-impurity-channel transistors (LICT's) by Aoki, M., Ishii, T., Yoshimura, T., Kiyota, Y., Iijima, S., Yamanaka, T., Kure, T., Ohyu, K., Nishida, T., Okazaki, S., Seki, K., Shimohigashi, K.

    Published in IEEE electron device letters (01-01-1992)
    “…0.1- mu m CMOS devices using low-impurity-channel transistors (LICTs) with dual-polysilicon gates have been fabricated by nondoped epitaxial growth technology,…”
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    Journal Article
  10. 10

    The origin of variable retention time in DRAM by Mori, Y., Ohyu, K., Okonogi, K., Yamada, R.

    “…To investigate the origin of DRAM variable retention time (VRT), we use test structures and carefully measure the time dependence of leakage current in DRAM…”
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    Conference Proceeding
  11. 11

    Advanced process device technology for 0.3- mu m high-performance bipolar LSIs by Tamaki, Y., Shiba, T., Kure, T., Ohyu, K., Nakamura, T.

    Published in IEEE transactions on electron devices (01-06-1992)
    “…A new method is developed for forming shallow emitter/bases, collectors, and graft bases suitable for high-performance 0.3- mu m bipolar LSIs. Fabricated 0.5-…”
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    Journal Article
  12. 12

    Channel length and width dependence of hot-carrier hardness in fluorinated MOSFETs by Nishioka, Y., Ohyu, K., Ohji, Y., Ma, T.-P.

    Published in IEEE electron device letters (01-12-1989)
    “…A study of the interface degradation caused by channel-hot-electron (CHE) and substrate-hot-electron (SHE) injection in fluorinated MOSFETs and in…”
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    Journal Article
  13. 13

    Improvement of SiO 2 /Si Interface Properties Utilising Fluorine Ion Implantation and Drive-in Diffusion by Ohyu, Kiyonori, Itoga, Toshihiko, Nishioka, Yasushiro, Natsuaki, Nobuyoshi

    Published in Japanese Journal of Applied Physics (01-06-1989)
    “…Thermal drive-in diffusion of ion-implanted F atoms has been employed to fluorinate SiO 2 /Si interfaces and thereby improve their electrical properties. The…”
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    Journal Article
  14. 14

    Radiation hardened micron and submicron MOSFETs containing fluorinated oxides by Nishioka, Y., Ohyu, K., Ohji, Y., Kato, M., da Silva, E.F., Ma, T.P.

    “…The generation of interface traps and oxide trapped charge in fluorinated MOSFETs and MOS capacitors has been found to depend strongly on the amount of…”
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    Journal Article Conference Proceeding
  15. 15

    Radiation effects on fluorinated field oxides and associated devices by Nishioka, Y., Itoga, T., Ohyu, K., Kato, M., Ma, T.-P.

    “…Fluorine has been introduced into the LOCOS field oxide by high-energy (2-MeV) F implantation and subsequent annealing at 950 degrees C for 60 min. Improved…”
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    Journal Article Conference Proceeding
  16. 16

    Lattice strain design in W/WN/poly-Si gate DRAM for improving data retention time by Okonogi, K., Ohyu, K., Toda, A., Kobayashi, H.

    “…A lattice strain design based on a novel model drastically improves the data retention property of DRAMs fabricated through a polymetal gate (W/WN/Poly-Si)…”
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    Conference Proceeding
  17. 17

    Hot-electron damage-resistant Si-gate submicrometer MOSFETs with a fluorinated oxide by Nishioka, Y., Ohji, Y., Ohyu, K., Mukai, K., Ma, T.P.

    Published in IEEE transactions on electron devices (01-11-1989)
    “…It has been reported previously (see E.F. da Silva, Jr. et al., 1987) that, by introducing minute amounts of fluorine in thermal SiO/sub 2/, the reliability of…”
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    Journal Article
  18. 18

    Comparison of TiSi2 and WSI2 Silicided Shallow Junctions for Sub-Micron CMOSs by Kobayashi, Nobuyoshi, Hashimoto, Naotaka, Ohyu, Kiyonori, Kaga, Toru, Iwata, Seiichi

    “…With the decrease of the junction depth of sub-micron CMOS devices, the development of low-resistivity shallow junctions is much needed. Self-aligned silicided…”
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    Conference Proceeding