Search Results - "Ohmacht, M."

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  1. 1

    A 1.3-GOPS parallel DSP for high-performance image-processing applications by Hinrichs, W., Wittenburg, J.P., Lieske, H., Kloos, H., Ohmacht, M., Pirsch, P.

    Published in IEEE journal of solid-state circuits (01-07-2000)
    “…A programmable digital signal processor (DSP) for real-time image processing is presented that combines the concepts of single-instruction multiple-data (SIMD)…”
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    Journal Article
  2. 2

    The eDRAM based L3-cache of the BlueGene/L supercomputer processor node by Ohmacht, M., Hoenicke, D., Haring, R., Gara, A.

    “…BlueGene/L is a supercomputer consisting of 64K dual-processor system-on-a-chip compute nodes, capable of delivering an arithmetic peak performance of…”
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    Conference Proceeding
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    Influences of object based segmentation onto multimedia hardware architectures by Ohmacht, M., Wittenburg, J., Pirsch, P.

    “…This paper describes essential differences in the video coding part of recent multimedia communication schemes (as the MPEG-4 standard being currently under…”
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    Conference Proceeding
  5. 5

    Parallel implementation of medium level algorithms on a monolithic ASIMD multiprocessor by Kneip, J., Ohmacht, M., Wittenburg, J.P., Pirsch, P.

    “…The efficient implementation of algorithms with irregular data access or control-flow on a parallel SIMD processor requires specific architectural measures…”
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    Conference Proceeding
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    HiPAR-DSP: a parallel VLIW RISC processor for real time image processing applications by Wittenburg, J.P., Ohmacht, M., Kneip, J., Hinrichs, W., Pirsch, P.

    “…Derived from a thorough analysis of a wide class of image processing algorithms' properties, a parallel RISC architecture has been developed. The architecture…”
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    Conference Proceeding
  7. 7

    Creating the BlueGene/L supercomputer from low-power SoC ASICs by Bright, A.A., Ellavsky, M.R., Gara, A., Haring, R.A., Kopcsay, G.V., Lembach, R.F., Marcella, J.A., Ohmacht, M., Salapura, V.

    “…An overview of the design aspects of the BlueGene/L chip, the heart of the BlueGene/L supercomputer, is presented. Following an SoC approach, processors,…”
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    Conference Proceeding
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    A 1.3 GOPS parallel DSP for high performance image processing applications by Hinrichs, W., Wittenburg, J.P., Lieske, H., Kloos, H., Ohmacht, M., Kneip, J., Ronner, K., Pirsch, P.

    “…In this paper, a programmable DSP for real time image processing is presented that combines the concepts of VLIW and SIMD with a high utilization of parallel…”
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    Conference Proceeding
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