Search Results - "Ogiue, K."

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  1. 1

    Perspective on BiCMOS VLSIs by Kubo, M., Masuda, I., Miyata, K., Ogiue, K.

    Published in IEEE journal of solid-state circuits (01-02-1988)
    “…A high-performance BiCMOS technology (Hi-BiCMOS) and its applications to VLSIs are described. By combining bipolar and CMOS devices in unit circuits of VLSIs,…”
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    Journal Article
  2. 2

    An experimental soft-error-immune 64-kbit 3-ns ECL bipolar RAM by Yamaguchi, K., Nanbu, H., Kanetani, K., Homma, N., Nakamura, T., Ohhata, K., Uchida, A., Ogiue, K.

    Published in IEEE journal of solid-state circuits (01-10-1989)
    “…An experimental soft-error-immune 64-kbit 3-ns ECL RAM has been developed. This high performance is achieved by using a soft-error-immune…”
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    Journal Article
  3. 3

    An 8 ns 256 K BiCMOS RAM by Tamba, N., Miyaoka, S., Odaka, M., Ogiue, K., Yamada, K., Ikeda, T., Hirao, M., Higuchi, H., Uchida, H.

    Published in IEEE journal of solid-state circuits (01-08-1989)
    “…A 256 K word*1 bit emitter-coupled logic (ECL) RAM, which achieves an 8 ns address access time, less than 400 mW power consumption at 50 MHz operation, and 150…”
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  4. 4

    High-speed BiCMOS technology with a buried twin well structure by Ikeda, T., Watanabe, A., Nishio, Y., Masuda, I., Tamba, N., Odaka, M., Ogiue, K.

    Published in IEEE transactions on electron devices (01-06-1987)
    “…A buried twin well and polysilicon emitter structure is developed for high-speed BiCMOS VLSI's. A bipolar transistor of high cutoff frequency (f T = 4 GHz) and…”
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  5. 5

    Complex Space Forms Immersed in Complex Space Forms by Nakagawa, H., Ogiue, K.

    “…We determine all the isometric immersions of complex space forms into complex space forms. Our results can be considered as the local version of a well-known…”
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  6. 6

    A 7-ns/350-mW 64-kbit ECL-compatible RAM by Miyaoka, S., Odaka, M., Ogiue, K., Ikeda, T., Suzuki, M., Higuchi, H., Hirao, M.

    Published in IEEE journal of solid-state circuits (01-10-1987)
    “…A 7-ns 350-mW, 64-kbit ECL RAM was developed using 1.3-/spl mu/m high-performance bipolar-CMOS (Hi-BiCMOS) technology, in which a bipolar transistor of 7-GHz…”
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  7. 7

    Ultra-thin Ta2O5dielectric film for high-speed bipolar memories by Nishioka, Y., Homma, N., Shinriki, H., Mukai, K., Yamaguchi, K., Uchida, A., Higeta, K., Ogiue, K.

    Published in IEEE transactions on electron devices (01-09-1987)
    “…A new capacitor technology, with extremely thin (5.3-20 nm) Ta 2 O 5 film deposition and weak-spot oxidation, is developed to realize high capacitance and high…”
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  8. 8

    Isotropic Immersions and Veronese Manifolds by Itoh, T., Ogiue, K.

    “…An n-dimensional Veronese manifold is defined as a minimal immersion of an n-sphere of curvature n/2(n + 1) into an {n(n + 2)/2 - 1}-dimensional unit sphere…”
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  9. 9

    A 16K-Bit Static IIL RAM with 25-ns Access Time by Inabe, Y., Hayashi, T., Kawarada, K., Miwa, H., Ogiue, K.

    Published in IEEE journal of solid-state circuits (01-04-1982)
    “…A 16 384 X 1-bit RAM with 25-ns access time, 600 -mW power dissipation, and 33-mm/sup 2/ chip size has been developed. Excellent speed-power performance with…”
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  10. 10

    A 16K-bit static IIL RAM with 25-ns access time by Inabe, Y., Hayashi, T., Kawarada, K., Miwa, H., Ogiue, K.

    Published in IEEE transactions on electron devices (01-04-1982)
    “…A 16 384 × 1-bit RAM with 25-ns access time, 600-mW power dissipation, and 33-mm 2 chip size has been developed. Excellent speed-power performance with high…”
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  11. 11

    13-ns, 500-mW, 64-kbit ECL RAM using Hi-BiCMOS technology by Ogiue, K., Odaka, M., Miyaoka, S., Masuda, I., Ikeda, T., Tonomura, K.

    Published in IEEE journal of solid-state circuits (01-10-1986)
    “…The development is discussed for a 13-ns, 500-mW, 16K word/spl times/4-bit emitter-coupled logic (ECL) RAM using high-performance bipolar CMOS (Hi-BiCMOS)…”
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  12. 12

    A pair of bipolar memory LSI chips for mainframe computers by Hotta, A., Ogiue, K., Mitsusada, K., Yamaguchi, K., Inadchi, M., Hinai, M.

    Published in IEEE journal of solid-state circuits (01-10-1979)
    “…A pair of bipolar memory chips has been developed. One is an LSI consisting of a 3072 bit RAM and 470 logic gates on the same chip. It has a typical address…”
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  13. 13

    A 3.5-ns, 2-W, 20-mm/SUP 2/, 16-kbit ECL bipolar RAM by Homma, N., Yamaguchi, K., Nanbu, H., Kanetani, K., Nishioka, Y., Uchida, A., Ogiue, K.

    Published in IEEE journal of solid-state circuits (01-10-1986)
    “…A 3.5-ns emitter-coupled logic (ECL) 16-kbit bipolar RAM with a power dissipation of 2 W, a cell size of 495 /spl mu/m/SUP 2/, and a chip size of 20 mm/SUP 2/…”
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    Ultra-thin Ta sub(2)O sub(5) dielectric film for high-speed bipolar memories by Nishioka, Y, Homma, N, Shinriki, H, Mukai, K, Yamaguchi, K, Uchida, A, Higeta, K, Ogiue, K

    Published in IEEE transactions on electron devices (01-01-1987)
    “…A new capacitor technology, with extremely thin (5.3-20 nm) Ta sub(2)O sub(5)film deposition and weak-spot oxidation, is developed to realize high capacitance…”
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    Journal Article
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