Impact of parasitic resistance and silicon layer thickness scaling for strained-silicon MOSFETs on relaxed Si1-xGex virtual substrate

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Bibliographic Details
Main Authors:	KAWASAKI, Hirohisa, OHUCHI, Kazuya, AOKI, Nobutoshi, KANEMURA, Takahisa, HAGISHNW, Daisuke, FUJIWARA, Makoto, INABA, Satoshi, ISHIRNARU, Kazunari, NAGASHIMA, Naoki, ISHIUCHI, Hidemi, OISHI, Amane, FUJII, Osamu, TSUJII, Hideji, ISHIDA, Tatsuya, KASAI, Kunihiro, OKAYAMA, Yasunori, KOJIMA, Kenji, ADACHI, Kanna
Format:	Conference Proceeding
Language:	English
Published:	Piscataway NJ IEEE 2004
Subjects:	Applied sciences Design. Technologies. Operation analysis. Testing Electronic equipment and fabrication. Passive components, printed wiring boards, connectics Electronics Exact sciences and technology Integrated circuits Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Transistors Performance evaluation Inverter Semiconductor alloys MOSFET Short channel Optimization Tensile stress Stress relaxation Direct current Complementary MOS technology Strained layer Parasitic resistance Delay time Miniaturization Electrical characteristic
Online Access:	Get full text
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Description
ISBN:	0780386841 9780780386846
DOI:	10.1109/IEDM.2004.1419098