Search Results - "Nowak, Edward J."

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  1. 1

    Challenges and Limitations of CMOS Scaling for FinFET and Beyond Architectures by Razavieh, Ali, Zeitzoff, Peter, Nowak, Edward J.

    “…Scaling trends of FinFET architecture, with focus on Front-End-of-Line (FEOL), and Middle-of-Line (MOL) device parameters, is systematically investigated. It…”
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    Journal Article
  2. 2

    Crystallographic-Orientation-Dependent Gate-Induced Drain Leakage in Nanoscale MOSFETs by Pandey, R K, Murali, K V R M, Furkay, S S, Oldiges, P J, Nowak, E J

    Published in IEEE transactions on electron devices (01-09-2010)
    “…The efficient and successful realization of low-power semiconductor devices demands, among other things, the ability to quantitatively model and minimize…”
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    Journal Article
  3. 3

    A Novel Technique for Probing the Vertical Component of FinFET Source Resistance by Wang, Peng, Yu, Mickey, Cave, Nigel, Nowak, Edward J.

    Published in IEEE transactions on electron devices (01-12-2021)
    “…We propose and demonstrate, with hardware, the first experimental technique to measure a vertical component of FinFET source resistance. Forward bias is…”
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    Journal Article
  4. 4

    Modeling and Characterization of Gate Leakage in High-K Metal Gate Technology-Based Embedded DRAM by Bajaj, Mohit, Pandey, Rajan K., De, Sandip, Sathaye, Ninad D., Jayaraman, Balaji, Krishnan, Rishikesh, Goyal, Puneet, Furkay, Stephen S., Nowak, Edward J., Iyer, Subramanian S., Murali, Kota V. R. M.

    Published in IEEE transactions on electron devices (01-12-2013)
    “…We report experimental characterization and modeling of direct and trap-assisted tunneling (TAT) in high-K metal gate (HKMG)-based access transistor and deep…”
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    Journal Article
  5. 5

    Modeling of Variation in Submicrometer CMOS ULSI Technologies by Springer, S.K., Lee, S., Lu, N., Nowak, E.J., Plouchart, J.-O., Watts, J.S., Williams, R.Q., Zamdmer, N.

    Published in IEEE transactions on electron devices (01-09-2006)
    “…The scaling of semiconductor technologies from 90- to 45-nm nodes highlights the need for accurate and predictive compact models that address the regime where…”
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    Journal Article
  6. 6

    Physiological and anatomical responses to water deficits in the CAM epiphyte Tillandsia ionantha (Bromeliaceae) by Nowak, E.J, Martin, C.E

    Published in International journal of plant sciences (01-11-1997)
    “…Although physiological responses to drought have been examined in several species of epiphytic bromeliads, few have included a comprehensive methodological…”
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    Journal Article
  7. 7

    Can macroscopic oxide thickness uniformity improve oxide reliability? by Wu, E.Y., Nowak, E.J., Vollertsen, R.-P.

    Published in IEEE electron device letters (01-08-2000)
    “…In this work, we investigated both experimentally and numerically the impact of macroscopic oxide thickness uniformity on Weibull breakdown characteristics for…”
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    Journal Article
  8. 8

    MOSFET technology for low-voltage/low-power applications by Foty, D.P., Nowak, E.J.

    Published in IEEE MICRO (01-06-1994)
    “…Certain limits influence MOSFET technology in low-voltage applications. When we reduce the power supply voltage in modern short-channel devices, both active…”
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    Journal Article
  9. 9

    Titanium silicide/silicon nonohmic contact resistance for NFET's, PFET's, diffused resistors, and NPN's in a BiCMOS technology by Hook, T.B., Mann, R.W., Nowak, E.J.

    Published in IEEE transactions on electron devices (01-04-1995)
    “…Self-aligned titanium silicide is often used to minimize the polysilicon and diffusion sheet resistances. Current is delivered to the channel of FET's, the…”
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    Journal Article
  10. 10

    Turning silicon on its edge [double gate CMOS/FinFET technology] by Nowak, E.J., Aller, I., Ludwig, T., Kim, K., Joshi, R.V., Ching-Te Chuang, Bernstein, K., Puri, R.

    Published in IEEE circuits and devices magazine (01-01-2004)
    “…Double-gate devices will enable the continuation of CMOS scaling after conventional scaling has stalled. DGCMOS/FinFET technology offers a tactical solution to…”
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    Journal Article
  11. 11

    Improved effective switching current (IEFF+) and capacitance methodology for CMOS circuit performance prediction and model-to-hardware correlation by Xiaojun Yu, Shu-jen Han, Zamdmer, N., Jie Deng, Nowak, E.J., Rim, K.

    “…New effective drive current I EFF + methodologies are demonstrated in this paper to address predictability of circuit performance across wide Vt range and…”
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    Conference Proceeding
  12. 12

    Self-Consistent and Efficient Electro-Thermal Analysis for Poly/Metal Gate FinFETs by Kumar, S., Joshi, R.V., Ching-Te Chuang, Keunwoo Kim, Murthy, J.Y., Schonenberg, K.T., Nowak, E.J.

    “…A self-consistent and efficient computational 3D modeling methodology for analyzing thermal and electrical transport in nano-scale devices is developed. The…”
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    Conference Proceeding
  13. 13

    45 nm SOI and Beyond - Getting to a General Purpose Technology by Iyer, S.S., Nowak, E.J.

    Published in 2007 IEEE International SOI Conference (01-10-2007)
    “…SOI technology has taken power/performance benefits of CMOS beyond those of bulk-CMOS technology in the arena of high-performance applications, including 4.7…”
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    Conference Proceeding
  14. 14

    Weibull breakdown characteristics and oxide thickness uniformity by Wu, E.Y., Nowak, E.J., Vollertsen, R.-P., Han, L.-K.

    Published in IEEE transactions on electron devices (01-12-2000)
    “…In this work, we investigated both experimentally and numerically the impact of macroscopic oxide thickness uniformity on Weibull breakdown characteristics for…”
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    Journal Article
  15. 15

    A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology by Joshi, R.V., Keunwoo Kim, Williams, R.Q., Nowak, E.J., Ching-Te Chuang

    “…This paper describes back-gate biasing scheme using independent-gate controlled asymmetrical (n + /p + polysilicon gates) FinFETs devices and its applications…”
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    Conference Proceeding
  16. 16
  17. 17

    Compact modeling and simulation of PD-SOI MOSFETs: Current status and challenges by Jung-Suk Goo, Williams, R.Q., Workman, G.O., Qiang Chen, Sungjae Lee, Nowak, E.J.

    “…This paper reviews the status and challenges of the modeling partially-depleted silicon-on-insulator transistors. Many challenges stem from the floating-body…”
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    Conference Proceeding
  18. 18

    Scaling planar silicon devices by Ching-Te Chuang, Bernstein, K., Joshi, R.V., Puri, R., Kim, K., Nowak, E.J., Ludwig, T., Aller, I.

    Published in IEEE circuits and devices magazine (01-01-2004)
    “…The generation-over-generation scaling of critical CMOS technology parameters is ultimately bound by nonscalable limitations, such as the thermal voltage and…”
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    Journal Article
  19. 19

    Ultimate CMOS ULSI performance by Nowak, E.J.

    “…Ultra-Large-Scale Integration (ULSI) CMOS technology is advancing beyond the realm of conventional scaling theory, requiring a new approach to the problem of…”
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    Conference Proceeding
  20. 20

    Performance, Reliability, and Supply Voltage Reduction, with the Addition of Temperature as a Design Variable by Foty, Daniel P., Nowak, Edward J.

    “…In any technology design, there rarely are "absolute" decisions that must be made. Instead, a variety of variables and choices must be evaluated to arrive at…”
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    Conference Proceeding