Search Results - "Norchip 2007"

QCA-LG: A tool for the automatic layout generation of QCA combinational circuits by Teodosio, T., Sousa, L.

“…Quantum-dot Cellular Automata (QCA) is a promising successor for CMOS transistor technology, while allowing the implementation of logic circuits using quantum…”
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A 3rd-order current-mode continuous-time filter in 65 nm CMOS by Uhrmann, H., Zimmermann, H.

“…A 3 rd -order continuous-time current-mode filter in 65 nm CMOS technology with a switchable cut-off frequency between 1.1 MHz and 4.4 MHz for software defined…”
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An 8-bit 10 kS/s 0.18 μm CMOS SAR ADC for RFID applications with sensing capabilities by Marjonen, J., Pesonen, N., Vermesan, O., Aberg, M., Oja, A., Rustad, H., Rusu, C., Enoksson, P.

“…An 25-muW 1.8V 8-bit 10 kS/s successive approximation (SAR) analog to digital converter (ADC) was designed and fabricated in a 0.18 mum CMOS technology for…”
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LMS-based identification and compensation of timing mismatches in a two-channel time-interleaved analog-to-digital converter by Saleem, S., Vogel, C.

“…A time-interleaved ADC (TIADC) increases the overall sampling rate by combining multiple slow ADCs. However, the performance of a TIADC suffers from several…”
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A z-domain model and analysis of phase-domain all-digital phase-locked loops by Mendel, S., Vogel, C.

“…In this paper a comprehensive z-domain model of all-digital phase-locked loops (ADPLLs) is derived. The model accounts for phase and frequency signals and thus…”
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Region-based routing algorithm for Network-on-Chip architectures by Schonwald, T., Bringmann, O., Rosenstiel, W.

“…In this paper, we present a novel approach for a region-based extension for a fully adaptive and fault-tolerant routing algorithm for Network-on-Chips (NoCs)…”
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Seven subthreshold flip-flop cells by Alstad, H.P., Aunet, S.

“…For ultra-low-power applications, operating the transistors in their subthreshold region is an effective way of reducing the power dissipation of a circuit…”
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Power optimized partial product reduction interconnect ordering in parallel multipliers by Oskuii, S.T., Kjeldsberg, P.G.

“…When designing the reduction tree of a parallel multiplier, we can exploit a large intrinsic freedom for the interconnection order of partial products. The…”
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On-chip digitally trimmable voltage reference by Spilka, R., Hirth, M., Hilber, G., Ostermann, T.

“…We present an on-chip digitally trimmable voltage reference which allows the realization of a constant reference voltage with only a maximal deviation of +/-…”
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High CMRR and low THD current-mode instrumentation amplifier using current inversion technique by Babaei, B., Mirzakuchaki, S.

“…The current-mode instrumentation amplifier based on second-generation current conveyors (CCII) offers many benefits over conventional instrumentation amplifier…”
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Defect tolerant ganged CMOS minority gate by Djupdal, A., Haddow, P.C.

“…Production defects, resulting in faulty transistors, provide a challenge for the semiconductor industry in terms of reduced Yield. As defect densities are…”
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Modeling capacitive links for broadband inter-chip communication by Viitala, O., Flak, J., Lindfors, S.

“…This paper presents the modeling of a close-proximity communication link with a lumped circuit representation. The inter-chip data transfer is performed via…”
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Performance analysis of BMC and Decision Units in the differential analog Viterbi decoder by Maunu, J., Laiho, M., Paasio, A.

“…In modern high-speed telecommunication systems a direct analog approach enables the A/D converter to be excluded from the Viterbi decoder implementation and…”
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Custom topology generation for network-on-chip by Stuart, M.B., Sparso, J.

“…This paper compares simulated annealing and tabu search for generating custom topologies for applications with periodic behaviour executing on a…”
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Design of a fourth-order continuous-time filter for UWB receivers by Xi Zhu, Moritz, J., Yichuang Sun

“…The design and implementation of a CMOS current- mode fourth-order Butterworth continuous-time leap-frog (LF) multiple loop feedback (MLF) lowpass filter is…”
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Decimation filter for a low-power sensor-interface system by Laulainen, E., Kosunen, M., Koskinen, L., Paavola, M., Halonen, K.

“…The presented decimator was designed to decimate a delta- sigma A/D-converter as part of a sensor-interface system for a three axis accelerometer. The…”
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A GaN HEMT power amplifier with variable gate bias for envelope and phase signals by Cijvat, E., Tom, K., Faulkner, M., Sjoland, H.

“…This paper describes the design, simulation and measurement of a GaN power amplifier suitable for envelope and phase signal combination. The low-frequency…”
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Impact of polar transmitter imperfections on UTRA LTE uplink performance by Priyanto, B.E., Sorensen, T.B., Jensen, O.K., Larsen, T., Kolding, T., Mogensen, P.

“…The polar transmitter is an alternative RF transmitter architecture solution to achieve a high-efficiency power amplifier. In this paper the impact of polar…”
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Design of A 7-bit, 200MS/s, 2mW pipelined ADC with switched open-loop amplifiers in a 65nm CMOS technology by Wulff, C., Ytterdal, T.

“…We present the design of a 7-bit 200 MS/s pipelined ADC with switched open-loop amplifiers in a 65 nm CMOS technology. As a result of turning off the open-loop…”
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Asynchronous design of networks-on-chip by Sparso, J.

“…The Network-on-chip concept has evolved as a solution to a broad range of problems related to the design of complex systems-on-chip (SoC) with tenths or…”
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