A new floating gate cell structure with a silicon-nitride cap layer for sub-20 nm NAND flash memory

A new cell structure of NAND memory devices, which employs an additional nitride layer between the top of a floating gate (FG) and inter-poly dielectrics (IPD), is devised to lesson a high electric field on the FG top edges during program. The cell structure is proved to be promising in sub-20 nm NA...

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Bibliographic Details
Published in:	2010 Symposium on VLSI Technology pp. 127 - 128
Main Authors:	Kwang Soo Seol, Heesoo Kang, Jaeduk Lee, Hyunsuk Kim, Byungkyu Cho, Dohyun Lee, Yong-Lack Choi, Nok-Hyun Ju, Changmin Choi, SungHoi Hur, Jungdal Choi, Chilhee Chung
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01-06-2010
Subjects:	cell structure Electric fields Flash memory IPD field crowding Leakage current Logic gates NAND Periodic structures Silicon compounds sub-20 nm Voltage measurement
Online Access:	Get full text
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Summary:	A new cell structure of NAND memory devices, which employs an additional nitride layer between the top of a floating gate (FG) and inter-poly dielectrics (IPD), is devised to lesson a high electric field on the FG top edges during program. The cell structure is proved to be promising in sub-20 nm NAND generation in terms of larger program window, better endurance, and more robust data retention, which are obtained by decreasing a leakage current of IPD relating with the electric field on the FG top edges.
ISBN:	9781424454518 1424454514
ISSN:	0743-1562
DOI:	10.1109/VLSIT.2010.5556197