Search Results - "Nohava, J.C."

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  1. 1

    High temperature performance and operation of HFETs by Wilson, C.D., O'Neill, A.G., Baier, S.M., Nohava, J.C.

    Published in IEEE transactions on electron devices (01-02-1996)
    “…The high temperature performance of Al/sub 0.75/Ga/sub 0.25/As/In/sub 0.25/Ga/sub 0.75/As/GaAs Complementary Heterojunction FETs (CHFETs) is reported between…”
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    Journal Article
  2. 2

    A 500-MHz 1616 complex multiplier using self-aligned gate GaAs heterostructure FET technology by Akinwande, A.I., MacTaggart, I.R., Betz, B.K., Grider, D.E., Lange, T.H., Nohava, J.C., Tetzlaff, D.E., Arch, D.K.

    Published in IEEE journal of solid-state circuits (01-10-1989)
    “…A 16*16-bit complex multiplier using self-aligned gate GaAs heterostructure FET technology has been demonstrated. The multiplier uses a modified Booth's…”
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    Journal Article
  3. 3

    AlGaAs/InGaAs/GaAs quantum well doped channel heterostructure field effect transistors by Ruden, P.P., Shur, M., Akinwande, A.I., Nohava, J.C., Grider, D.E., Baek, J.

    Published in IEEE transactions on electron devices (01-10-1990)
    “…The results of experimental and theoretical studies of pseudomorphic AlGaAs/InGaAs/GaAs quantum-well doped-channel heterostructure field effect transistors…”
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    Journal Article
  4. 4

    A self-aligned gate III-V heterostructure FET process for ultrahigh-speed digital and mixed analog/digital LSI/VLSI circuits by Akinwande, A.I., Ruden, P.P., Vold, P.J., Han, C.-J., Grider, D.E., Narum, D.H., Nohava, T.E., Nohava, J.C., Arch, D.K.

    Published in IEEE transactions on electron devices (01-10-1989)
    “…A planar ion-implanted self-aligned gate process for the fabrication of high-speed digital and mixed analog/digital LSI/VLSI integrated circuits is reported. A…”
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    Journal Article
  5. 5

    A 4 kbit synchronous static random access memory based upon delta-doped complementary heterostructure insulated gate field effect transistor technology by Grider, D.E., Mactaggart, I.R., Nohava, J.C., Stronczer, J.J., Ruden, P.P., Nohava, T.E., Fulkerson, D., Tetzlaff, D.E.

    “…Delta-doped pseudomorphic In/sub y/Ga/sub 1-y/As channel complementary heterostructure insulated gate field effect transistor (C-HIGFET) technology has been…”
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    Conference Proceeding
  6. 6

    Delta-doped complementary heterostructure FETs with high Y-value pseudomorphic In/sub 1/Ga/sub 1-y/As channels for ultra-low-power digital IC applications by Grider, D.E., Ruden, P.P., Nohava, J.C., Mactaggart, I.R., Stronczer, J.J., Nohava, T.E., Swirhun, S.S.

    “…The authors report on the device and circuit performance of delta-doped complementary heterostructure insulated gate field effect transistors (C-HIGFETs) which…”
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    Conference Proceeding
  7. 7

    Development of static random access memories using complementary heterostructure insulated gate field effect transistor technology by Grider, D.E., Akinwande, A.I., Mactaggart, R., Ruden, P.P., Nohava, J.C., Nohava, T.E., Breezley, J.E., Joslyn, P., Tetzlaff, D.

    “…A complementary heterostructure insulated gate field effect transistor (c-HIGFET) technology has been developed which is capable of operating at high speeds…”
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    Conference Proceeding
  8. 8

    A high performance (Al,Ga)As/GaAs MODFET butterfly adder chip for FFT computation by Akinwande, A.I., Betz, B.K., MacTaggart, I.R., Grider, D.E., Narum, D.H., Lange, T.H., Nohava, T.E., Nohava, J.C., Tetzlaff, D., Arch, D.K.

    “…A report is presented on a butterfly adder chip for high-speed computation of fast Fourier transforms (FFTs). It was fabricated using a 1- mu m self-aligned…”
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    Conference Proceeding
  9. 9

    Complementary III-V heterostructure FETs for low power integrated circuits by Akinwande, A.I., Ruden, P.P., Grider, D.E., Nohava, J.C., Nohava, T.E., Joslyn, P.D., Breezley, J.E.

    “…The authors report on a complementary III-V heterostructure FET (HFET) technology that makes use of high AlAs mole fraction (Al,Ga)As barrier layers to reduce…”
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    Conference Proceeding