Search Results - "Niu, Dimin"

Overcoming the challenges of crossbar resistive memory architectures by Cong Xu, Dimin Niu, Muralimanohar, Naveen, Balasubramonian, Rajeev, Tao Zhang, Shimeng Yu, Yuan Xie

“…The scalability of DRAM faces challenges from increasing power consumption and the difficulty of building high aspect ratio capacitors. Consequently, emerging…”
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Practical Near-Data-Processing Architecture for Large-Scale Distributed Graph Neural Network by Huang, Linyong, Zhang, Zhe, Li, Shuangchen, Niu, Dimin, Guan, Yijin, Zheng, Hongzhong, Xie, Yuan

“…Graph Neural Networks have drawn tremendous attention in the past few years due to their convincing performance and high interpretability in various…”
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OpSparse: A Highly Optimized Framework for Sparse General Matrix Multiplication on GPUs by Du, Zhaoyang, Guan, Yijin, Guan, Tianchan, Niu, Dimin, Huang, Linyong, Zheng, Hongzhong, Xie, Yuan

“…Sparse general matrix multiplication (SpGEMM) is an important and expensive computation primitive in many real-world applications. Due to SpGEMM's inherent…”
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Accelerating CPU-Based Sparse General Matrix Multiplication With Binary Row Merging by Du, Zhaoyang, Guan, Yijin, Guan, Tianchan, Niu, Dimin, Zheng, Hongzhong, Xie, Yuan

“…Sparse general matrix multiplication (SpGEMM) is a fundamental building block for many real-world applications. Since SpGEMM is a well-known memory-bounded…”
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Impact of process variations on emerging memristor by Dimin Niu, Yiran Chen, Cong Xu, Yuan Xie

“…The memristor, known as the fourth basic two-terminal circuit element, has attracted many research interests since the first real device was developed by HP…”
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DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric by Mingyu Gao, Delimitrou, Christina, Dimin Niu, Malladi, Krishna T., Hongzhong Zheng, Brennan, Bob, Kozyrakis, Christos

“…The DRAM-Based Reconfigurable Acceleration Fabric (DRAF) uses commodity DRAM technology to implement a bit-level, reconfigurable fabric that improves area…”
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Low power multi-level-cell resistive memory design with incomplete data mapping by Dimin Niu, Qiaosha Zou, Cong Xu, Yuan Xie

“…Phase change memory (PCM) has been widely studied as a potential DRAM alternative. The multi-level cell (MLC) can further increase the memory density and…”
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Understanding the trade-offs in multi-level cell ReRAM memory design by Xu, Cong, Niu, Dimin, Muralimanohar, Naveen, Jouppi, Norman P., Xie, Yuan

“…Resistive Random Access Memory (ReRAM) is one of the most promising emerging memory technologies as a potential replacement for DRAM memory and/or NAND Flash…”
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Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis by Yibo Chen, Dimin Niu, Yuan Xie, Chakrabarty, K

“…Three-dimensional (3D) ICs promise to overcome barriers in interconnect scaling by leveraging fast, dense inter-die vias, thereby offering benefits of improved…”
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DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric by Mingyu Gao, Delimitrou, Christina, Dimin Niu, Malladi, Krishna T., Hongzhong Zheng, Brennan, Bob, Kozyrakis, Christos

“…FPGAs are a popular target for application-specific accelerators because they lead to a good balance between flexibility and energy efficiency. However, FPGA…”
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Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach by Xu, Cong, Zheng, Yang, Niu, Dimin, Zhu, Xiaochun, Kang, Seung H., Xie, Yuan

“…Spin-transfer torque random access memory (STT-RAM) is a promising candidate for universal memory due to its speed, scalability, and non-volatility. A wide…”
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Energy-efficient multi-level cell phase-change memory system with data encoding by Jue Wang, Xiangyu Dong, Guangyu Sun, Dimin Niu, Yuan Xie

“…Phase-change memory (PCM) is one of the most promising technologies among emerging non-volatile memories. Recently, the technology of multi-level cell (MLC)…”
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A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement by Guangyu Sun, Yongsoo Joo, Yibo Chen, Dimin Niu, Yuan Xie, Yiran Chen, Hai Li

“…In recent years, many systems have employed NAND flash memory as storage devices because of its advantages of higher performance (compared to the traditional…”
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SCOPE: a stochastic computing engine for DRAM-based in-situ accelerator by Li, Shuangchen, Glova, Alvin Oliver, Hu, Xing, Gu, Peng, Niu, Dimin, Malladi, Krishna T., Zheng, Hongzhong, Brennan, Bob, Xie, Yuan

“…Memory-centric architecture, which bridges the gap between compute and memory, is considered as a promising solution to tackle the memory wall and the power…”
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SBAC: A statistics based cache bypassing method for asymmetric-access caches by Chao Zhang, Guangyu Sun, Peng Li, Tao Wang, Dimin Niu, Yiran Chen

“…Asymmetric-access caches with emerging technologies, such as STT-RAM and RRAM, have become very competitive designs recently. Since the write operations…”
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DRISA: a DRAM-based Reconfigurable In-Situ Accelerator by Li, Shuangchen, Niu, Dimin, Malladi, Krishna T., Zheng, Hongzhong, Brennan, Bob, Xie, Yuan

“…Data movement between the processing units and the memory in traditional von Neumann architecture is creating the "memory wall" problem. To bridge the gap, two…”
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iPIM: Programmable In-Memory Image Processing Accelerator Using Near-Bank Architecture by Gu, Peng, Xie, Xinfeng, Ding, Yufei, Chen, Guoyang, Zhang, Weifeng, Niu, Dimin, Xie, Yuan

“…Image processing is becoming an increasingly important domain for many applications on workstations and the datacenter that require accelerators for high…”
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Design of cross-point metal-oxide ReRAM emphasizing reliability and cost by Dimin Niu, Cong Xu, Muralimanohar, Naveen, Jouppi, Norman P., Yuan Xie

“…Metal-Oxide Resistive Random Access Memory (ReRAM) technology is gaining popularity due to its superior write bandwidth, high density, and low operating power…”
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Flatfish: A Reinforcement Learning Approach for Application-Aware Address Mapping by Li, Xingchen, Yuan, Zhihang, Guan, Yijin, Sun, Guangyu, Zhang, Tao, Wei, Rongshan, Niu, Dimin

“…The DRAM performance has become a critical bottleneck of modern computing systems. Prior studies have proposed various optimization techniques on address…”
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DLUX: A LUT-Based Near-Bank Accelerator for Data Center Deep Learning Training Workloads by Gu, Peng, Xie, Xinfeng, Li, Shuangchen, Niu, Dimin, Zheng, Hongzhong, Malladi, Krishna T., Xie, Yuan

“…The frequent data movement between the processor and the memory has become a severe performance bottleneck for deep neural network (DNN) training workloads in…”
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