Search Results - "Nikolić, Borivoje"

BAG2: A process-portable framework for generator-based AMS circuit design by Chang, Eric, Han, Jaeduk, Bae, Woorham, Wang, Zhongkai, Narevsky, Nathan, NikoliC, Borivoje, Alon, Elad

“…We present BAG2, a framework for the development of process-portable Analog and Mixed Signal (AMS) circuit generators. Such generators are parametrized design…”
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An Adaptable and Scalable Generator of Distributed Massive MIMO Baseband Processing Systems by Dai, Yue, Rasekh, Maryam Eslami, Mirfarshbafan, Seyed Hadi, Liew, Harrison, Gallyas-Sanhueza, Alexandra, Dunn, James, Madhow, Upamanyu, Studer, Christoph, Nikolić, Borivoje

“…This paper presents an algorithm-adaptable, scalable, and platform-portable generator for massive multiple-input multiple-output (MIMO) baseband processing…”
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Performance and Area Scaling Benefits of FD-SOI Technology for 6-T SRAM Cells at the 22-nm Node by Changhwan Shin, Min Hee Cho, Tsukamoto, Yasumasa, Bich-Yen Nguyen, Mazuré, Carlos, Nikolić, Borivoje, Tsu-Jae King Liu

“…The performance and threshold voltage variability of fully depleted silicon-on-insulator (FD-SOI) MOSFETs are compared against those of conventional bulk…”
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Guest Editorial Introduction to the Special Issue on the 2022 Symposium on VLSI Circuits by Nikolic, Borivoje, Hamada, Mototsugu

“…This Special Issue of the IEEE Journal of Solid-State Circuits highlights some of the outstanding circuits papers presented at the Symposium on VLSI Technology…”
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Wireless Channel Dynamics and Robustness for Ultra-Reliable Low-Latency Communications by Swamy, Vasuki Narasimha, Rigge, Paul, Ranade, Gireeja, Nikolic, Borivoje, Sahai, Anant

“…Interactive, immersive, and other timing-critical applications demand ultra-reliable low-latency communication (URLLC). To build wireless communication systems…”
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Simpler, more efficient design by Nikolic, Borivoje

“…Design of custom integrated circuits has become prohibitively expensive for many application domains. As a result, these domains often choose to implement the…”
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AuRORA: A Full-Stack Solution for Scalable and Virtualized Accelerator Integration by Kim, Seah, Zhao, Jerry, Asanovic, Krste, Nikolic, Borivoje, Shao, Yakun Sophia

“…To meet the increasingly demanding compute requirements of modern workloads, systems on chip (SoCs) must provide an accelerator-rich hardware architecture and…”
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Analysis of the relationship between random telegraph signal and negative bias temperature instability by Tsukamoto, Yasumasa, Seng Oon Toh, Changhwan Shin, Mairena, Andrew, Tsu-Jae King Liu, Nikolić, Borivoje

“…Random telegraph signal (RTS) is shown to be an intrinsic component of the shift in MOSFET threshold voltage (V th ) due to bias temperature instability (BTI)…”
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A Self-Adjustable Clock Generator With Wide Dynamic Range in 28 nm FDSOI by Jaehwa Kwak, Nikolic, Borivoje

“…This work demonstrates a self-adjustable clock generator that closely tracks the voltage dependence of the critical path delay in a microprocessor. A tunable…”
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An Interference-Resilient Wideband Mixer-First Receiver With LO Leakage Suppression and I/Q Correlated Orthogonal Calibration by Wu, Charles, Yanjie Wang, Nikolic, Borivoje, Hull, Christopher

“…A mixer-first receiver design in 28-nm CMOS is discussed. An embedded 5-bit mixer digital-to-analog converter provides wideband tuneability to enhance device…”
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Analysis of Absorbing Sets and Fully Absorbing Sets of Array-Based LDPC Codes by Dolecek, L., Zhengya Zhang, Anantharam, V., Wainwright, M.J., Nikolic, B.

“…The class of low-density parity-check (LDPC) codes is attractive, since such codes can be decoded using practical message-passing algorithms, and their…”
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A Chisel Generator for Standardized 3-D Die-to-Die Interconnects by Liew, Harrison, Sheikh, Farhana, Guo, Jong-Ru, Wu, Zuoguo, Nikolic, Borivoje

“…A 3-D heterogeneous integration (3-D-HI) is poised to enable a new era of high-performance integrated circuits via a multitude of benefits, including a…”
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An Efficient 10GBASE-T Ethernet LDPC Decoder Design With Low Error Floors by Zhengya Zhang, Anantharam, V., Wainwright, M.J., Nikolic, B.

“…A grouped-parallel low-density parity-check (LDPC) decoder is designed for the (2048,1723) Reed-Solomon-based LDPC (RS-LDPC) suitable for 10GBASE-T Ethernet. A…”
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A Variation-Tolerant, Sneak-Current-Compensated Readout Scheme for Cross-Point Memory Based on Two-Port Sensing Technique by Bae, Woorham, Yoon, Kyung Jean, Song, Taeksang, Nikolic, Borivoje

“…A variation-tolerant and sneak-current-free readout technique for cross-point non-volatile memory is presented. The proposed readout circuit has a sneak…”
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Characterization of Dynamic SRAM Stability in 45 nm CMOS by Toh, Seng Oon, Guo, Zheng, Liu, Tsu-Jae King, Nikolic, Borivoje

“…Optimization of SRAM yield using dynamic stability metrics has been evaluated in the past to ensure continued scaling of bitcell size and supply voltage in…”
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A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI by Wright, John Charles, Schmidt, Colin, Keller, Ben, Dabbelt, Daniel Palmer, Kwak, Jaehwa, Iyer, Vighnesh, Mehta, Nandish, Chiu, Pi-Feng, Bailey, Stevo, Asanovic, Krste, Nikolic, Borivoje

“…This work demonstrates a dual-core RISC-V system-on-chip (SoC) with integrated fine-grain power management. The 28-nm fully depleted silicon-on-insulator…”
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An FD/FDD transceiver with RX band thermal, quantization, and phase noise rejection and >64dB TX signal cancellation by Ramakrishnan, Sameet, Calderin, Lucas, Niknejad, Ali, Nikolic, Borivoje

“…A transceiver system with active cancellation of the TX signal for full duplex (FD) or frequency division duplex systems (FDD) is presented. A replica…”
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A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI by Zimmer, Brian, Lee, Yunsup, Puggelli, Alberto, Kwak, Jaehwa, Jevtic, Ruzica, Keller, Ben, Bailey, Steven, Blagojevic, Milovan, Chiu, Pi-Feng, Le, Hanh-Phuc, Chen, Po-Hung, Sutardja, Nicholas, Avizienis, Rimas, Waterman, Andrew, Richards, Brian, Flatresse, Philippe, Alon, Elad, Asanovic, Krste, Nikolic, Borivoje

“…This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC-DC (SC…”
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A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI by Keller, Ben, Cochet, Martin, Zimmer, Brian, Kwak, Jaehwa, Puggelli, Alberto, Yunsup Lee, Blagojevic, Milovan, Bailey, Stevo, Pi-Feng Chiu, Dabbelt, Palmer, Schmidt, Colin, Alon, Elad, Asanovic, Krste, Nikolic, Borivoje

“…This paper presents a RISC-V system-on-chip (SoC) with integrated voltage regulation, adaptive clocking, and power management implemented in a 28 nm fully…”
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Use of Phase Delay Analysis for Evaluating Wideband Circuits: An Alternative to Group Delay Analysis by Woorham Bae, Nikolic, Borivoje, Deog-Kyoon Jeong

“…A phase delay analysis is proposed against pursuing a flat group delay response for the design of wideband circuits. While it is believed that a large group…”
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