Search Results - "Nigam, T"

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  1. 1

    Challenges in the characterization and modeling of BTI induced variability in metal gate / High-k CMOS technologies by Kerber, A., Nigam, T.

    “…Large scale BTI data was collected on discrete MG/HK devices to discuss modeling challenges related to BTI induced variability. A fast, parallel BTI testing…”
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    Conference Proceeding
  2. 2

    Off-state TDDB in FinFET Technology and its Implication for Safe Operating Area by Toledano-Luque, M., Paliwoda, P., Nour, M., Kauerauf, T., Min, B., Bossu, G., Siddabathula, M., Nigam, T.

    “…Standard CMOS reliability has been focused on digital applications and the user profiles associated with these products. However, emerging applications in…”
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    Conference Proceeding
  3. 3

    A Novel HCI Reliability Model for RF/mmWave Applications in FDSOI Technology by Arfaoui, W., Bossu, G., Muhlhoff, A., Lipp, D., Manuwald, R., Chen, T., Nigam, T., Siddabathula, M.

    “…Although technology scaling to deep submicron enable higher degrees of semiconductor integration, highly integrated circuit have become increasingly sensitive…”
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    Conference Proceeding
  4. 4

    Optimized LDMOS Offering for Power Management and RF Applications by Cimino, S., Singh, J., Johnson, J. B., Zheng, W., Chen, Y., Liu, W., Srinivasan, P., Gonzales, O., Hauser, M., Koskinen, M., Nagahiro, K., Liu, Y., Min, B., Nigam, T., Squib, N.

    “…The suitability of a 12nm FinFET LDMOS offering toward a broad range of applications has been demonstrated. This work focuses on key reliability aspects with…”
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    Conference Proceeding
  5. 5

    Hierarchical High Sigma Monte Carlo Simulation of SRAM Vmin Shift by Parts for Automotive Grade Fail Rate Projection by karim, M. Ahosan ul, Balasubramanian, S., Peters, L., Fisher, K., Dyck, J., Song, Y., Luque, M., Higman, J., Nigam, T.

    “…We developed an infrastructure to simulate SRAM Vmin shift from time-zero (TO) to end-of-life (EOL) by parts utilizing the Hierarchical Monte Carlo tool under…”
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    Conference Proceeding
  6. 6

    Soft breakdown of ultra-thin gate oxide layers by Depas, M., Nigam, T., Heyns, M.M.

    Published in IEEE transactions on electron devices (01-09-1996)
    “…The dielectric breakdown of ultra-thin 3 nm and 4 nm SiO/sub 2/ layers used as a gate dielectric in poly-Si gate capacitors is investigated. The ultra-thin…”
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    Journal Article
  7. 7

    Understanding gate metal work function (mWF) impact on device reliability - A holistic approach by Srinivasan, P., Ranjan, R., Cimino, S., Zainuddin, A., Kannan, B., Pantisano, L., Mahmud, I., Dilliway, G., Nigam, T.

    “…The effect on device reliability mechanisms due to gate metal work function (mWF) in thin and thick gate oxide FinFETs is shown here. Lower BTI is noticed for…”
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    Conference Proceeding
  8. 8

    Impact of Transistor Level degradation on product reliability by Nigam, T.

    “…Product level lifetime margins, determined by HCI and BTI, are shrinking with scaling. Accurate device-level HCI degradation models, together with known BTI…”
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    Conference Proceeding
  9. 9

    Impact of charge trapping on the voltage acceleration of TDDB in metal gate/high-k n-channel MOSFETs by Kerber, A, Vayshenker, A, Lipp, D, Nigam, T, Cartier, E

    “…The root cause for the increase in the TDDB voltage acceleration with decreasing stress voltage in metal gate/high-k n-channel FETs is investigated. Using DC…”
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    Conference Proceeding
  10. 10

    On the properties of the gate and substrate current after soft breakdown in ultrathin oxide layers by Crupi, F., Degraeve, R., Groeseneken, G., Nigam, T., Maes, H.E.

    Published in IEEE transactions on electron devices (01-11-1998)
    “…In this work we have studied soft breakdown (SBD) in capacitors and nMOSFET's with 4.5-nm oxide thickness. It is shown that for larger area devices gate…”
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    Journal Article
  11. 11

    Bias temperature instability in scaled CMOS technologies: A circuit perspective by Kerber, A., Nigam, T.

    Published in Microelectronics and reliability (01-02-2018)
    “…Bias temperature instability has impacted scaling of conventional poly-Si/SiON CMOS technologies and remains a critical device reliability mechanism for metal…”
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    Journal Article
  12. 12

    Soft breakdown in ultrathin gate oxides: Correlation with the percolation theory of nonlinear conductors by Houssa, M., Nigam, T., Mertens, P. W., Heyns, M. M.

    Published in Applied physics letters (27-07-1998)
    “…The dielectric breakdown under constant current stressing of 4.2 nm SiO2 gate oxides is investigated. After soft breakdown, which corresponds to an anomalous…”
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    Journal Article
  13. 13

    Nature and location of interface traps in RF LDMOS due to hot carriers by Nigam, T., Shibib, A., Xu, S., Safar, H., Steinberg, L.

    Published in Microelectronic engineering (01-04-2004)
    “…In this paper, the nature and location of hot carrier induced defects is studied for N-channel LDMOS (Laterally Diffused MOS) transistors. These devices are…”
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    Journal Article Conference Proceeding
  14. 14

    Addressing reliability challenges in advance nodes for commercial and automotive application by Nigam, T., Paliwoda, P., Wang, X., Kerber, A.

    “…Building in reliability is critical during technology development, as we continue scaling or incorporating additional functionality. In this paper Front End Of…”
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    Conference Proceeding
  15. 15

    Fast characterization of the Static Noise Margin degradation of cross-coupled inverters and correlation to BTI instabilities in MG/HK devices by Kerber, A, Pimparkar, N, Balasubramanian, S, Nigam, T, McMahon, W, Cartier, E

    “…A fast BTI characterization setup is introduced to study the Static Noise Margin (SNM) of cross-coupled inverters using metal gate / high-k devices. It is…”
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    Conference Proceeding
  16. 16

    Definition of dielectric breakdown for ultra thin (<2 nm) gate oxides by Depas, M, Nigam, T, Heyns, M.M

    Published in Solid-state electronics (01-05-1997)
    “…The different stages of wear-out of an ultra thin 1.7 nm SiO 2 during a time dependent dielectric breakdown test of a poly-Si gate metal-oxide-silicon…”
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    Journal Article
  17. 17

    The vertical replacement-gate (VRG) MOSFET by Hergenrother, J.M., Oh, Sang-Hyun, Nigam, T., Monroe, D., Klemens, F.P., Kornblit, A.

    Published in Solid-state electronics (01-07-2002)
    “…We have fabricated and demonstrated a new device called the vertical replacement-gate (VRG) MOSFET. This is the first MOSFET ever built in which: (1) all…”
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    Journal Article
  18. 18

    Temperature dependence and conduction mechanism after analog soft breakdown by Nigam, T., Martin, S., Abusch-Magder, D.

    “…The current conduction after analog soft breakdown (A-SBD) is studied as a function of temperature for NMOS and PMOS transistors. Unlike direct tunneling, a…”
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    Conference Proceeding
  19. 19

    Application of CVS and VRS method for correlation of logic CMOS wear out to discrete device degradation based on ring oscillator circuits by Kerber, A., Nigam, T.

    Published in 2016 IEEE Symposium on VLSI Technology (01-06-2016)
    “…Device level reliability margins are reducing for advanced MG/HK technology nodes, hence it is essential to comprehend product level reliability margin using…”
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    Conference Proceeding
  20. 20

    Hot carrier degradation and time-dependent dielectric breakdown in oxides by Groeseneken, G., Degraeve, R., Nigam, T., Van den bosch, G., Maes, H.E.

    Published in Microelectronic engineering (1999)
    “…An overview is given of our present understanding of the main degradation mechanisms acting during hot carrier and high field stress of gate oxides. A brief…”
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    Journal Article Conference Proceeding