Search Results - "Nicolaidis, M"

Time redundancy based soft-error tolerance to rescue nanometer technologies by Nicolaidis, M.

“…The increased operating frequencies, geometry shrinking and power supply reduction that accompany the process of very deep submicron scaling, affect the…”
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Carry checking/parity prediction adders and ALUs by Nicolaidis, M.

“…In this paper, we present efficient self-checking implementations valid for all existing adder and arithmetic and logic unit (ALU) schemes (e.g., ripple carry,…”
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Upset hardened memory design for submicron CMOS technology by Calin, T., Nicolaidis, M., Velazco, R.

“…A novel design technique is proposed for storage elements which are insensitive to radiation-induced single-event upsets. This technique is suitable for…”
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On-Line Testing for VLSI--A Compendium of Approaches by Nicolaidis, M, Zorian, Y

“…This paper presents an overview of a comprehensive collection of on-line testing techniques for VLSI. Such techniques are for instance: self-checking design,…”
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Theory of transparent BIST for RAMs by Nicolaidis, M.

“…I present the theoretical aspects of a technique called transparent BIST for RAMs. This technique applies to any RAM test algorithm and transforms it into a…”
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Cost reduction and evaluation of a temporary faults detecting technique by Anghel, L., Nicolaidis, M.

“…IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are…”
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A diversified memory built-in self-repair approach for nanotechnologies by Nicolaidis, M., Achouri, N., Anghel, L.

“…Memory built in self repair (BISR) is gaining importance since several years. Because defect densities are increasing with submicron scaling, more advanced…”
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Fault secure property versus strongly code disjoint checkers by Nicolaidis, M.

“…The final checker of a self-checking system is an embedded double-rail checker (the partial checkers have in general two outputs). The self-testing or the…”
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New methods for evaluating the impact of single event transients in VDSM ICs by Alexandrescu, D., Anghel, L., Nicolaidis, M.

“…This work considers a SET (single event transient) fault simulation technique to evaluate the probability that a transient pulse, born in the combinational…”
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An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories by Gill, Balkaran, Nicolaidis, Michael, Wolff, Francis, Papachristou, Chris, Garverick, Steven

“…In this paper we propose a new Built in Current Sensor (BICS) to detect single event upsets in SRAM. The BICS is designed and validated for 100nm process…”
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A fault-tolerant deadlock-free adaptive routing for on chip interconnects by Chaix, F, Avresky, D, Zergainoh, N-E, Nicolaidis, M

“…Future applications will require processors with many cores communicating through a regular interconnection network. Meanwhile, the Deep submicron technology…”
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Fail-safe interfaces for VLSI: theoretical foundations and implementation by Nicolaidis, M.

“…This paper presents the design of strongly fail-safe interfaces which transform binary signals, generated by a system with error detection capabilities and…”
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Reliability threats in VDSM - shortcomings in conventional test and fault tolerance alternatives by Nicolaidis, M.

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On-line testing for VLSI: state of the art and trends by Nicolaidis, Michael

“…This paper discusses the state of the art and future trends of on-line testing techniques for VLSI. It cautions that emerging technological constraints and…”
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Design for soft-error robustness to rescue deep submicron scaling by Nicolaidis, M.

“…Error detecting and correcting code based memory design, self-checking design, VLSI-level retry architectures, perturbation hardened design, tools for…”
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Simulating Single Event Transients in VDSM ICs for Ground Level Radiation by Alexandrescu, Dan, Anghel, Lorena, Nicolaidis, Michael

“…Issue Title: Special Issue on the Third IEEE Latin-American Test Workshop This work considers a SET (single event transient) fault simulation technique to…”
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Iterative Diagnosis Approach for ECC-Based Memory Repair by Papavramidou, Panagiota, Nicolaidis, Michael

“…In modern SoCs embedded memories should be protected by ECC against field failures to achieve acceptable reliability. They should also be repaired after…”
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On-line testing for VLSI by Nicolaidis, M.

“…A large variety of on-line testing techniques for VLSI was developed in the past and are still enriched by new developments. They can respond efficiently to…”
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Memory Defect Tolerance Architectures for Nanotechnologies by Nicolaidis, Michael, Anghel, Lorena, Achouri, Nadir

“…Issue Title: Special Issue on On-Line-Testing and Fault Tolerance Memory Built In Self Repair (BISR) is gaining importance since several years. Because defect…”
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Single event effects in static and dynamic registers in a 0.25 mu m CMOS technology by Faccio, F, Kloukinas, K, Marchioro, A, Calin, T, Cosculluela, J, Nicolaidis, M, Velazco, R

“…We have studied single event effects in static and dynamic registers designed in a quarter micron CMOS process. In our design, we systematically used…”
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