Search Results - "Niazmand, Behrad"

QoSinNoC: Analysis of QoS-Aware NoC Architectures for Mixed-Criticality Applications by Avramenko, Serhiy, Azad, Siavoosh Payandeh, Esposito, Stefano, Niazmand, Behrad, Violante, Massimo, Raik, Jaan, Jenihhin, Maksim

“…Multi-Processor Systems-on-Chip (MPSoCs) have been a clear new trend in processor-based systems design. General purpose MPSoC designers have turned to the…”
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A loss aware scalable topology for photonic on chip interconnection networks by Reza, Akram, Sarbazi-Azad, Hamid, Khademzadeh, Ahmad, Shabani, Hesam, Niazmand, Behrad

“…The demand for robust computation systems has led to the increment of the number of processing cores in current chips. As the number of processing cores…”
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Comprehensive performance and robustness analysis of 2D turn models for network-on-chips by Azad, Siavoosh Payandeh, Niazmand, Behrad, Janson, Karl, Kogge, Thilo, Raik, Jaan, Jervan, Gert, Hollstein, Thomas

“…Routing algorithms play an important role in Network-on-Chip (NoC) based System-on-Chips. Turn model based routing disallows some of the turns in order to…”
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Enabling Secure MPSoC Dynamic Operation through Protected Communication by Azad, Siavoosh Payandeh, Niazmand, Behrad, Jervan, Gert, Sepulveda, Johanna

“…High parallelism and flexibility have turned the Multi-Processors System-on-Chip (MPSoCs) into one of the key enabling technologies for new computational…”
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From RTL Liveness Assertions to Cost-Effective Hardware Checkers by Hariharan, Ranganathan, Ghasempouri, Tara, Niazmand, Behrad, Raik, Jaan

“…This paper proposes a methodology for producing a set of high quality hardware checkers from Register-Transfer Level (RTL) assertions. Assertion Based…”
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LiD-CAT: A Lightweight Detector for Cache ATtacks by Reinbrecht, Cezar, Hamdioui, Said, Taouil, Mottaqiallah, Niazmand, Behrad, Ghasempouri, Tara, Raik, Jaan, Sepulveda, Johanna

“…Cache attacks are one of the most wide-spread and dangerous threats to embedded computing systems' security. A promising approach to detect such attacks at…”
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Design and Verification of Secure Cache Wrapper Against Access-Driven Side-Channel Attacks by Niazmand, Behrad, Payandeh Azad, Siavoosh, Jervan, Gert, Sepulveda, Johanna

“…While caches are shared resources used to speedup the execution of applications, including the execution of cryptographic applications, their use can expose…”
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An Automatic Approach to Evaluate Assertions' Quality Based on Data-Mining Metrics by Ghasempouri, Tara, Payandeh Azad, Siavoosh, Niazmand, Behrad, Raik, Jaan

“…The effectiveness of Assertion-Based Verification (ABV) depends on the quality of assertions. Assertions can be manually or automatically generated. In both…”
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Upgrading QoSinNoC: Efficient Routing for Mixed-Criticality Applications and Power Analysis by Avramenko, Serhiy, Azad, Siavoosh Payandeh, Niazmand, Behrad, Violante, Massimo, Raik, Jaan, Jenihhin, Maksim

“…Multi-processor system-on-chip (MPSoC) devices are a well known replacement of single-core devices. Some industries, like avionic, are particularly sensitive…”
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A Hierarchical Approach for Devising Area Efficient Concurrent Online Checkers by Niazmand, Behrad, Payandeh Azad, Siavoosh, Ghasempouri, Tara, Raik, Jaan, Jervan, Gert

“…The shrinking feature size in semiconductor technology beyond the sub-micron domain negatively affects the reliability of digital circuits and makes them more…”
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AWAIT: An Ultra-Lightweight Soft-Error Mitigation Mechanism for Network-on-Chip Links by Janson, Karl, Pihlak, Rene, Azad, Siavoosh Payandeh, Niazmand, Behrad, Jervan, Gert, Raik, Jaan

“…Networks-on-Chip have become a widely accepted communication paradigm for many-core Systems-on-Chip. However, with the ever-shrinking transistor size, the…”
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Handling of SETs on NoC Links by Exploitation of Inherent Redundancy in Circular Input Buffers by Janson, Karl, Pihlak, Rene, Azad, Siavoosh Payandeh, Niazmand, Behrad, Jervan, Gert, Raik, Jaan

“…The miniaturization of nanometer technologies beyond the sub-micron domain has jeopardized the reliability of on-chip network links, making them more…”
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Logic-based implementation of fault-tolerant routing in 3D network-on-chips by Niazmand, Behrad, Azad, Siavoosh Payandeh, Flich, Jose, Raik, Jaan, Jervan, Gert, Hollstein, Thomas

“…The susceptibility of on-chip communication links and on-chip routers to faults has guided the research towards focusing on fault-tolerance aspects of 2D and…”
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Mixed-criticality NoC partitioning based on the NoCDepend dependability technique by Hollstein, Thomas, Azad, Siavoosh Payandeh, Kogge, Thilo, Niazmand, Behrad

“…The deployment of mixed-criticality applications on NoC (Network-on-Chip)-based MPSoC (Multiprocessor System-on-Chip) platforms requires a stringent protection…”
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From online fault detection to fault management in Network-on-Chips: A ground-up approach by Azad, Siavoosh Payandeh, Niazmand, Behrad, Janson, Karl, George, Nevin, Oyeniran, Adeboye Stephen, Putkaradze, Tsotne, Kaur, Apneet, Raik, Jaan, Jervan, Gert, Ubar, Raimund, Hollstein, Thomas

“…Due to the ongoing miniaturization of silicon technology beyond the sub-micron domain and the trend of integrating ever more components on a single chip, the…”
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Fault-resilient NoC router with transparent resource allocation by Putkaradze, Tsotne, Azad, Siavoosh Payandeh, Niazmand, Behrad, Raik, Jaan, Jervan, Gert

“…The current trend of aggressive technology scaling results in a decrease in system's reliability. This motivates investigation of fault-resilient architectures…”
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Automated area and coverage optimization of minimal latency checkers by Azad, Siavoosh Payandeh, Niazmand, Behrad, Sandhu, Apneet Kaur, Raik, Jaan, Jervan, Gert, Hollstein, Thomas

“…With the scaling of silicon technology beyond the sub-micron domain, the probability of the system being exposed to different sources of faults increases…”
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Automated minimization of concurrent online checkers for Network-on-Chips by Saltarelli, Pietro, Niazmand, Behrad, Hariharan, Ranganathan, Raik, Jaan, Jervan, Gert, Hollstein, Thomas

“…The paper introduces automated minimization of a set of concurrent online checkers for Network-on-Chips (NoCs) under given fault detection quality constraints…”
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SoCDep2: A framework for dependable task deployment on many-core systems under mixed-criticality constraints by Azad, Siavoosh Payandeh, Niazmand, Behrad, Ellervee, Peeter, Raik, Jaan, Jervan, Gert, Hollstein, Thomas

“…In this paper, an open-source framework for task deployment of mixed-critical and non-critical applications under dependability constraints in Network-on-Chip…”
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Holistic Approach for Fault-Tolerant Network-on-Chip based Many-Core Systems by Azad, Siavoosh Payandeh, Niazmand, Behrad, Raik, Jaan, Jervan, Gert, Hollstein, Thomas

“…In this paper we describe a holistic approach for Fault-Tolerant Network-on-Chip (NoC) based many-core systems that incorporates a System Health Monitoring…”
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