Search Results - "Nane, Razvan"

A Survey and Evaluation of FPGA High-Level Synthesis Tools by Nane, Razvan, Sima, Vlad-Mihai, Pilato, Christian, Jongsok Choi, Fort, Blair, Canis, Andrew, Yu Ting Chen, Hsuan Hsiao, Brown, Stephen, Ferrandi, Fabrizio, Anderson, Jason, Bertels, Koen

“…High-level synthesis (HLS) is increasingly popular for the design of high-performance and energy-efficient heterogeneous systems, shortening time-to-market and…”
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On the Implementation of Computation-in-Memory Parallel Adder by Hoang Anh Du Nguyen, Lei Xie, Taouil, Mottaqiallah, Nane, Razvan, Hamdioui, Said, Bertels, Koen

“…Today's computer architectures suffer from many challenges, such as the near end of CMOS downscaling, the memory/communication bottleneck, the power wall, and…”
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SDC-based Resource Constrained Scheduling for Quantum Control Architectures by Nane, Razvan

“…Instruction scheduling is a key transformation in backend compilers that take an untimed description of an algorithm and assigns time slots to the algorithm's…”
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Skeleton-Based Synthesis Flow for Computation-in-Memory Architectures by Yu, Jintao, Nane, Razvan, Ashraf, Imran, Taouil, Mottaqiallah, Hamdioui, Said, Corporaal, Henk, Bertels, Koen

“…Memristor-based Computation-in-Memory (CIM) is one of the emerging architectures for next-generation Big Data problems. Its design requires a radically new…”
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High-Level Synthesis in the Delft Workbench Hardware/Software Co-design Tool-Chain by Nane, Razvan, Sima, Vlad Mihai, Pham Quoc, Cuong, Goncalves, Fernando, Bertels, Koen

“…High-level synthesis (HLS) is an automated design process that deals with the generation of behavioral hardware descriptions from high-level algorithmic…”
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An Image Processing VLIW Architecture for Real-Time Depth Detection by Iorga, Dan, Nane, Razvan, Lu, Yi, Van Dalen, Edwin, Bertels, Koen

“…Numerous applications for mobile devices require 3D vision capabilities, which in turn require depth detection since this enables the evaluation of an object's…”
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Controlling a complete hardware synthesis toolchain with LARA aspects by Cardoso, João M.P., Carvalho, Tiago, Coutinho, José G.F., Nobre, Ricardo, Nane, Razvan, Diniz, Pedro C., Petrov, Zlatko, Luk, Wayne, Bertels, Koen

“…The synthesis and mapping of applications to configurable embedded systems is a notoriously complex process. Design-flows typically include tools that have a…”
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An Evaluation and Comparison of GPU Hardware and Solver Libraries for Accelerating the OPM Flow Reservoir Simulator by Qiu, Tong Dong, Thune, Andreas, Blatt, Markus, Rustad, Alf Birger, Nane, Razvan

“…Realistic reservoir simulation is known to be prohibitively expensive in terms of computation time when increasing the accuracy of the simulation or by…”
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Sparstition: A Partitioning Scheme for Large-Scale Sparse Matrix Vector Multiplication on FPGA by Sigurbergsson, Bjorn, Hogervorst, Tom, Qiu, Tong Dong, Nane, Razvan

“…Sparse Matrix Vector Multiplication (SpMV) is a key kernel in various domains, that is known to be difficult to parallelize efficiently due to the low spatial…”
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Hardware Acceleration of HPC Computational Flow Dynamics using HBM-enabled FPGAs by Hogervorst, Tom, Qiu, Tong Dong, Marchiori, Giacomo, Birger, Alf, Blatt, Markus, Nane, Razvan

“…ACM Transactions on Reconfigurable Technology and Systems, Volume 15, Issue 2, June 2022 Scientific computing is at the core of many High-Performance Computing…”
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Skeleton-based design and simulation flow for Computation-in-Memory architectures by Yu Jintao, Nane, Razvan, Haron, Adib, Hamdioui, Said, Corporaal, Henk, Bertels, Koen

“…Memristor-based Computation-in-Memory is one of the emerging architectures proposed to deal with Big Data problems. The design of such architectures requires a…”
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Parallel matrix multiplication on memristor-based computation-in-memory architecture by Haron, Adib, Yu, Jintao, Nane, Razvan, Taouil, Mottaqiallah, Hamdioui, Said, Bertels, Koen

“…One of the most important constraints of today's architectures for data-intensive applications is the limited bandwidth due to the memory-processor…”
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Computation-in-memory based parallel adder by Du Nguyen, Hoang Anh, Xie, Lei, Taouil, Mottaqiallah, Nane, Razvan, Hamdioui, Said, Bertels, Koen

“…Today's computing systems suffer from memory/communication bottleneck, resulting in energy and performance inefficiency. This makes them incapable to solve…”
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DWARV 2.0: A CoSy-based C-to-VHDL hardware compiler by Nane, R., Sima, V., Olivier, B., Meeuws, R., Yankova, Y., Bertels, K.

“…In the last decade, a considerable amount of effort was spent on raising the implementation level of hardware systems by automatically extracting the…”
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Low-Cost Software Control-Flow Error Recovery by Nazarian, Ghazaleh, Nane, Razvan, Gaydadjiev, Georgi N.

“…In modern safety-critical embedded systems reliability and performance are two important criteria. In many systems based on off-the-shelf processors software…”
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A lightweight speculative and predicative scheme for hardware execution by Nane, R., Sima, V., Bertels, K.

“…If-conversion is a known software technique to speedup applications containing conditional expressions and targeting processors with predication support…”
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IP-XACT extensions for Reconfigurable Computing by Nane, R., van Haastregt, S., Stefanov, T., Kienhuis, B., Sima, V. M., Bertels, K.

“…Many of today's embedded multiprocessor systems are implemented as heterogeneous systems, consisting of hardware and software components. To automate the…”
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