Search Results - "Nakamoto, Mark"

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  1. 1

    Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs by Xiaoxia Wu, Wei Zhao, Nakamoto, M., Nimmagadda, C., Lisk, D., Gu, S., Radojcic, R., Nowak, M., Yuan Xie

    “…Reducing interconnect delay and power consumption has become a major concern in deep submicron designs. 3-D technologies have been proposed as a promising…”
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    Journal Article
  2. 2

    Simulation methodology and flow integration for 3D IC stress management by Nakamoto, M, Radojcic, R, Wei Zhao, Dasarapu, V K, Karmarkar, A P, Xiaopeng Xu

    “…A new methodology to bridge package and silicon domain simulations is demonstrated using a new data file to facilitate stress information exchange. The flow…”
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    Conference Proceeding
  3. 3

    Numerical Model for Understanding Failure Mechanism of Back End of Line (BEOL) in Bump Shear by Wang, Wei, Zhao, Wei, Nakamoto, Mark, Schwarz, Mark, He, Dongming, Zhang, Xuefeng, Zhao, Lily, Syed, Ahmer

    “…With the increasing requirement for advanced technology nodes in high-performance devices, low-K (LK), ultralow-K (ULK) and extreme low K (ELK) dielectric…”
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    Conference Proceeding
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    Mechanical stress management for electrical chip-package interaction (e-CPI) by Wei Zhao, Nakamoto, Mark, Ramachandran, Vidhya, Radojcic, Riko

    “…e-CPI has emerged as a new risk in modern chip design as silicon dies become increasingly thinner and packages become increasingly more complex. e-CPI is…”
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    Conference Proceeding
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    A complete and automatic advanced model verification platform for 32nm technology and beyond by Yanfeng Li, Radojcic, R., Nakamoto, M., Fatehi, J., Geng Zhang, Xisheng Zhang, Kang, J.F.

    “…Variability from different sources such as layout-dependent effect has been a main obstacle against aggressive design rule and shrinking corner margins in 45…”
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    Conference Proceeding
  7. 7

    Design for manufacturability for fabless manufactuers by Radojcic, Riko, Perry, Dan, Nakamoto, Mark

    Published in IEEE solid state circuits magazine (01-01-2009)
    “…When a company designs and sells ICs but outsources their manufacture, design for manufacturability poses special challenges. It is clear that these DfM…”
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    Journal Article
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    A complete stress enhancement model development and verification platform for 32nm technology and beyond by Yanfeng Li, Nengyong Zhu, Miao Li, Yanjun Wu, Qiang Chen, Shuang Cai, Radojcic, R, Nakamoto, M

    “…Variability from different sources such as layout-dependent effects due to strain has been a main obstacle against aggressive design rules and reducing corner…”
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    Conference Proceeding
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