Search Results - "Naganuma, J."

Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level by Iwasaki, H., Naganuma, J., Nitta, K., Nakamura, K., Yoshitome, T., Ogura, M., Nakajima, Y., Tashiro, Y., Onishi, T., Ikeda, M., Minami, T., Endo, M., Yashima, Y.

“…This paper proposes a new architecture for VASA, a single-chip MPEG-2 422P@HL CODEC LSI with multichip configuration for large scale processing beyond the HDTV…”
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New set-top box for interactive visual communication of home entertainment using MPEG-2 full-duplex CODEC LSI by Inamori, M., Iwasaki, H., Onishi, T., Ikeda, M., Naganuma, J., Yashima, Y.

“…This paper describes a new set-top box of interactive visual communication for home entertainment exploiting single-chip MPEG-2 CODEC LSI. The set-top box has…”
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Characteristics of aluminum substitution technology for self-aligned full metal gate nMOSFETs by Mishima, Y., Shido, H., Kurahashi, T., Nagata, T., Naganuma, J., Kudo, H., Nakamura, S.

“…We investigated self-aligned metal gate MOSFETs that feature an ideal low-resistance aluminum gate using aluminum substitution technology (AST). This…”
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A memory-based architecture for MPEG2 system protocol LSIs by Inamori, M., Naganuma, J., Endo, M.

“…This paper proposes a memory-based architecture implementing the MPEG2 system protocol large scale integrations (LSIs), and demonstrates its flexibility and…”
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SuperENC: MPEG-2 video encoder chip by Ikeda, M., Kondo, T., Nitta, K., Suguri, K., Yoshitome, T., Minami, T., Iwasaki, H., Ochiai, K., Naganuma, J., Endo, M., Tashiro, Y., Watanabe, H., Kobayashi, N., Okubo, T., Kasai, R.

“…Thanks to increased market acceptance of applications such as digital versatile disks (DVDs), HDTV, and digital satellite broadcasting, the MPEG-2 (Moving…”
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New set-top box for interactive visual communication of home entertainment using MPEG-2 full-duplex codec LSI by Inamori, M., Iwasaki, H., Onishi, T., Ikeda, M., Naganuma, J., Yashima, Y.

“…The paper describes a new interactive visual communication set-top box for home entertainment exploiting a single-chip MPEG-2 codec LSI. The set-top box has…”
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Single-chip MPEG-2 422P@HL CODEC LSI with multi-chip configuration for large scale processing beyond HDTV level by Iwasaki, I., Naganuma, J., Nitta, K., Nakamura, K., Yoshitome, T., Ogura, M., Nakajima, Y., Tashiro, Y., Onishi, T., Ikeda, M., Endo, M.

“…This paper proposes a new architecture for VASA, a single-chip MPEG-2 422P@HL CODEC LSI with multichip configuration for large scale processing beyond the HDTV…”
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A highly OR-parallel inference machine (Multi-ASCA) and its performance evaluation: an architecture and its load balancing algorithms by Naganuma, J., Ogura, T.

“…An architecture and its four load balancing algorithms for a highly OR-parallel inference machine are proposed, and its performance is evaluated in a…”
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An MPEG-2 video encoder LSI with scalability for HDTV based on three-layer cooperative architecture by Ikeda, M., Kondo, T., Nitta, K., Suguri, K., Yoshitome, T., Minami, T., Naganuma, J., Ohura, T.

“…This paper proposes a new architecture for a single-chip MPEG-2 video encoder with scalability for HDTV and demonstrates its flexibility and usefulness. The…”
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High-speed software-based platform for embedded software of a single-chip MPEG-2 video encoder LSI with HDTV scalability by Ochiai, K., Iwasaki, H., Naganuma, J., Endo, M., Ogura, T.

“…This paper proposes a high-speed software-based platform for embedded software and evaluates its benefits on a commercial MPEG-2 video encoder LSI with HDTV…”
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High-speed CAM-based architecture for a Prolog machine (ASCA) by Naganuma, J., Ogura, T., Yamada, S.-I., Kimura, T.

“…A content addressable memory (CAM)-based machine architecture is proposed for a high-speed Prolog machine. This Prolog machine attempts to speed up the total…”
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An MPEG-2 encoding PC card system for real-time mobile applications by Endo, M., Naganuma, J., Nakajima, Y., Ogura, T.

“…This paper describes an MPEG-2 real-time encoding Type-II PC card system for mobile applications. It incorporates a new hardware/software cooperative…”
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Single-Chip MPEG-2 422PL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level by Iwasaki, H, Naganuma, J, Nitta, K, Nakamura, K, Yoshitome, T, Ogura, M, Nakajima, Y, Tashiro, Y, Onishi, T, Ikeda, M, Minami, T, Endo, M, Yashima, Y

“…This paper proposes a new architecture for VASA, a single-chip MPEG-2 422PL CODEC LSI with multichip configuration for large scale processing beyond the HDTV…”
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A software-based H.264/AVC HDTV real-time interactive CODEC architecture using parallel processing by Sano, T., Ohnishi, T., Iwasaki, H., Kamikura, K., Naganuma, J.

“…This paper describes a software-based H.264/AVC HDTV real-time interactive CODEC architecture (named RISCA264-HD) using parallel processing. The RISCA264-HD…”
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A memory-based architecture for MPEG2 System protocol LSIs by Inamori, M., Naganuma, J., Wakabayashi, H., Endo, M.

“…This paper proposes a memory-based architecture implementing the MPEG2 System protocol LSIs, and demonstrates its flexibility and performance. The memory-based…”
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Conventional repair and operative stent-grafting for acute and chronic aortic dissection by Miyairi, Takeshi, Ninomiya, Mikio, Endoh, Munemoto, Naganuma, Junichi, Kotsuka, Yutaka, Takamoto, Shinichi

“…Conventional graft replacement of the ascending aorta and surgically endovascular stent-grafting of the proximal descending aorta were performed concomitantly…”
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Multi-reference and multi-block-size motion estimation with flexible mode selection for professional 4:2:2 H.264/AVC encoder LSI by Onishi, T, Sano, T, Nitta, K, Ikeda, M, Naganuma, J

“…We describe a multiple reference and multiple block size motion estimation (ME) hardware design for professional encoder LSIs, that supports H.264/AVC High…”
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Polling-based real-time software for MPEG2 System protocol LSIs by Naganuma, J., Endo, M.

“…This paper proposes polling-based real-time software for MPEG2 System protocol LSIs, which is a typical embedded and real-time system on a chip, and…”
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A distributed TS-MUX architecture for multi-chip extension beyond the HDTV level by Onishi, T., Ikeda, M., Naganuma, J., Endo, M., Yashima, Y.

“…This paper proposes a distributed stream multiplexing architecture for CODEC LSIs with multi-chip configuration, and demonstrates its scalability and…”
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An associative processor for logic programming languages by Naganuma, J., Ogura, T.

“…Proposes an associative processor architecture for logic programming languages, and specifically examines such architecture for a sequential language, Prolog,…”
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