Malware Detection Using Xilinx Software and Adaptive Test Pattern

This work introduces novel approaches to accelerate the production of deterministic test patterns for VLSI devices. These methods reduce the number of backtracking while requiring little processing effort, therefore improving the PODEM algorithm. This is accomplished by assigning additional signal l...

Full description

Saved in:

Bibliographic Details
Published in:	2023 9th International Conference on Advanced Computing and Communication Systems (ICACCS) Vol. 1; pp. 759 - 764
Main Authors:	Meivel, S., Nagaharipriya, S. K., Priyankadevi, P., Sangavi, S.
Format:	Conference Proceeding
Language:	English
Published:	IEEE 17-03-2023
Subjects:	Adaptive Generator Backtracking BIST Architecture Combinational circuits Life estimation PODEM Algorithm Robustness Sequential circuits Software algorithms Unique Sensitization Very large scale integration VLSI Circuits
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!

Description
Summary:	This work introduces novel approaches to accelerate the production of deterministic test patterns for VLSI devices. These methods reduce the number of backtracking while requiring little processing effort, therefore improving the PODEM algorithm. This is accomplished by assigning additional signal lines to the relevant signals, spotting errors earlier, and eliminating extra effort during test generation. These methods have been included into ATOM, a sophisticated ATPG device for combinational circuits. The test generation results for the benchmark circuits' ATOM as well as full scan versions showed how effective these strategies were at improving performance ATOM found all tested problems in a short period of time and proved that all overlapping faults were excessive with minimum backtracking
ISSN:	2575-7288
DOI:	10.1109/ICACCS57279.2023.10112911