Search Results - "NAINANI, Aneesh"

Germanium oxynitride gate interlayer dielectric formed on Ge(100) using decoupled plasma nitridation by Bhatt, Piyush, Chaudhuri, Krishnakali, Kothari, Shraddha, Nainani, Aneesh, Lodha, Saurabh

“…Germanium Oxynitride (GeON) gate interlayer (IL) dielectric formed using decoupled plasma nitridation (DPN) technique is compared with GeO2 and thermally…”
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Increase in current density for metal contacts to n-germanium by inserting TiO2 interfacial layer to reduce Schottky barrier height by Lin, J.-Y. Jason, Roy, Arunanshu M., Nainani, Aneesh, Sun, Yun, Saraswat, Krishna C.

“…Metal contacts to n-type Ge have poor performance due to the Fermi level pinning near the Ge valence band at metal/Ge interfaces. The electron barrier height…”
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Impact of fixed charge on metal-insulator-semiconductor barrier height reduction by Hu, Jenny, Nainani, Aneesh, Sun, Yun, Saraswat, Krishna C., Philip Wong, H.-S.

“…Recently, the insertion of ultrathin insulators to form metal-insulator-semiconductor (MIS) contacts has been used extensively to reduce the Schottky barrier…”
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High-Mobility Ge N-MOSFETs and Mobility Degradation Mechanisms by Kuzum, Duygu, Krishnamohan, Tejas, Nainani, Aneesh, Yun Sun, Pianetta, Piero A, Wong, H.-S Philip, Saraswat, Krishna C

“…Ge N-MOSFETs have exhibited poor drive currents and low mobility, as reported by several different research groups in the past. The major mechanisms behind…”
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Enhanced Ge n+/p Junction Performance Using Cryogenic Phosphorus Implantation by Bhatt, Piyush, Swarnkar, Prashant, Misra, Abhishek, Biswas, Jayeeta, Hatem, Christopher, Nainani, Aneesh, Lodha, Saurabh

“…In this paper, we present a detailed study of temperature-based ion implantation of phosphorus dopants in Ge for varying dose and anneal conditions through…”
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High Performance 400 °C p+/n Ge Junctions Using Cryogenic Boron Implantation by Bhatt, Piyush, Swarnkar, Prashant, Basheer, Firdous, Hatem, Christopher, Nainani, Aneesh, Lodha, Saurabh

“…We report high performance Ge p + /n junctions using a single, cryogenic (-100 °C) boron ion implantation process. High activation>4 × 10 20 cm -3 results in…”
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Fluorine passivation of vacancy defects in bulk germanium for Ge metal-oxide-semiconductor field-effect transistor application by Jung, Woo-Shik, Park, Jin-Hong, Nainani, Aneesh, Nam, Donguk, Saraswat, Krishna C.

“…Vacancy defects in germanium (Ge) adversely impact the electrical performance of Ge based metal-oxide-semiconductor field-effect transistor (MOSFET) in several…”
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Amelioration of interface state response using band engineering in III-V quantum well metal-oxide-semiconductor field-effect transistors by Yuan, Ze, Nainani, Aneesh, Bennett, Brian R., Brad Boos, J., Ancona, Mario G., Saraswat, Krishna C.

“…Performance degradation due to interfacial traps is generally considered as one of the main challenges for III-V metal-oxide-semiconductor…”
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Performance Improvement of One-Transistor DRAM by Band Engineering by Pal, A., Nainani, A., Gupta, S., Saraswat, K. C.

“…We propose a novel one-transistor (1T) quantum well (QW) DRAM with raised GaP source/drain. This novel device structure shows much better retention time and…”
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Study of piezoresistance under unixial stress for technologically relevant III-V semiconductors using wafer bending experiments by Nainani, Aneesh, Yum, Jung, Barnett, Joel, Hill, Richard, Goel, Niti, Huang, Jeff, Majhi, Prashant, Jammy, Raj, Saraswat, Krishna C.

“…In this work, effect of uniaxial stress is studied by wafer bending on p / n -channel candidates for III-V based complimentary logic. p -GaSb has 2× higher…”
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Optimization of the \hbox\hbox/ \hbox Interface and a High-Mobility GaSb pMOSFET by Nainani, A., Irisawa, T., Ze Yuan, Bennett, B. R., Boos, J. B., Nishi, Y., Saraswat, K. C.

“…While there have been many demonstrations on n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) in III-V semiconductors showing excellent…”
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on-State Performance Enhancement and Channel-Direction-Dependent Performance of a Biaxial Compressive Strained \hbox\hbox Quantum-Well pMOSFET Along \langle \hbox \rangle and \langle \hbox \rangle Channel Directions by Se-Hoon Lee, Nainani, Aneesh, Jungwoo Oh, Kanghoon Jeon, Kirsch, Paul D, Majhi, Prashant, Register, Leonard Franklin, Banerjee, Sanjay K, Jammy, Raj

“…pMOSFET performance of high Ge content (~50%) biaxial compressive strained SiGe heterostructure channel pMOSFETs is characterized, and performance between 〈110…”
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GeSn technology: Extending the Ge electronics roadmap by Gupta, S., Chen, R., Magyari-Kope, B., Hai Lin, Bin Yang, Nainani, A., Nishi, Y., Harris, J. S., Saraswat, K. C.

“…First principles study showed indicated band gap of Ge can be tuned by alloying with Sn and metastable GeSn alloys can be synthesized at or above room…”
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Fermi-level unpinning and low resistivity in contacts to n-type Ge with a thin ZnO interfacial layer by Paramahans Manik, Prashanth, Kesh Mishra, Ravi, Pavan Kishore, V., Ray, Prasenjit, Nainani, Aneesh, Huang, Yi-Chiau, Abraham, Mathew C., Ganguly, Udayan, Lodha, Saurabh

“…We report low resistance Ohmic contacts on n-Ge using a thin ZnO interfacial layer (IL) capped with Ti. A 350°C post metallization anneal is used to create…”
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Optimization of the Al2O3/GaSb Interface and a High-Mobility GaSb pMOSFET by NAINANI, Aneesh, IRISAWA, Toshifumi, ZE YUAN, BENNETT, Brian R, BRAD BOOS, J, NISHI, Yoshio, SARASWAT, Krishna C

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Epitaxially Defined FinFET: Variability Resistant and High-Performance Technology by Mittal, Sushant, Gupta, Shashank, Nainani, Aneesh, Abraham, Mathew C., Schuegraf, Klaus, Lodha, Saurabh, Ganguly, Udayan

“…FinFET technology is prone to suffer from line edge roughness (LER)-based V T variation with scaling. It also lacks a simple implementation of multiple V T…”
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Antimonide-Based Heterostructure p-Channel MOSFETs With Ni-Alloy Source/Drain by Ze Yuan, Kumar, Archana, Chien-Yu Chen, Nainani, Aneesh, Bennett, Brian R., Boos, John Brad, Saraswat, Krishna C.

“…In this letter, we study the formation and electrical properties of Ni-GaSb alloys by direct reaction of Ni with GaSb. It is found that several properties of…”
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Schottky barrier height reduction for metal/n-GaSb contact by inserting TiO2 interfacial layer with low tunneling resistance by Yuan, Ze, Nainani, Aneesh, Sun, Yun, Lin, J.-Y. Jason, Pianetta, Piero, Saraswat, Krishna C.

“…Fermi level pinning near GaSb valence band edge leads to high Schottky barrier height for metal/n-type GaSb contacts. However, this effect can be alleviated by…”
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Is strain engineering scalable in FinFET era?: Teaching the old dog some new tricks by Nainani, A., Gupta, S., Moroz, V., Munkang Choi, Yihwan Kim, Cho, Y., Gelatos, J., Mandekar, T., Brand, A., Er-Xuan Ping, Abraham, M. C., Schuegraf, K.

“…S/D epitaxy remains an effective source of strain engineering for both aggressively and conservatively scaled FinFETs. Not merging the S/D epitaxy between…”
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Addressing key challenges in 1T-DRAM: Retention time, scaling and variability - Using a novel design with GaP source-drain by Pal, Ashish, Nainani, Aneesh, Saraswat, Krishna C.

“…We propose a vertical gate all around 1-transistor DRAM cell with silicon channel and gallium phosphide source drain (GaP-SD) as a viable alternative to the…”
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