MPEG-2 4:2:2@HL encoder chip set

An MPEG-2 4:2:2@HL encoder chip set will be presented. It is composed of an encoder LSI [COD-LSI], a preprocessor LSI [PP-LSI], and a motion estimation LSI [ME3-LSI]. Scalable architecture allows a cascadable configuration for higher picture quality and higher resolutions. The encoder LSI, which is...

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Bibliographic Details
Published in:	2000 IEEE International Symposium on Circuits and Systems (ISCAS) Vol. 4; pp. 41 - 44 vol.4
Main Authors:	Sato, H., Ohira, H., Kazayama, M., Harada, A., Yoshimoto, M., Tanno, O., Kumaki, S., Ishibara, K., Hanami, A., Mutsumura, T.
Format:	Conference Proceeding
Language:	English
Published:	IEEE 2000
Subjects:	Cyclic redundancy check Discrete cosine transforms Encoding Hardware HDTV Large scale integration Motion estimation SDRAM Timing Transform coding
Online Access:	Get full text
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Summary:	An MPEG-2 4:2:2@HL encoder chip set will be presented. It is composed of an encoder LSI [COD-LSI], a preprocessor LSI [PP-LSI], and a motion estimation LSI [ME3-LSI]. Scalable architecture allows a cascadable configuration for higher picture quality and higher resolutions. The encoder LSI, which is the key to this chip set, employs advanced hybrid architecture with a 162 MHz media-processor core [D30V] and dedicated video processing hardware. It also has dual-communication-ports for a multi-chip configuration. With above architecture, a single encoder LSI can perform SDTV encoding, and only six chips can perform HDTV encoding.
ISBN:	9780780354821 0780354826
DOI:	10.1109/ISCAS.2000.858683