Search Results - "Mullinnix, S."

A 600-MHz VLIW DSP by Agarwala, S., Anderson, T., Hill, A., Ales, M.D., Damodaran, R., Wiley, P., Mullinnix, S., Leach, J., Lell, A., Gill, M., Rajagopal, A., Chachad, A., Agarwala, M., Apostol, J., Krishnan, M., Duc Bui, Quang An, Nagaraj, N.S., Wolf, T., Elappuparackal, T.T.

“…A 600-MHz VLIW digital signal processor (DSP) delivers 4800 MIPS, 2400 (16 b) or 4800 (8 b) million multiply accumulates (MMACs) at 0.3 mW/MMAC (16 b). The…”
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A 1.25GHz 0.8W C66x DSP Core in 40nm CMOS by Damodaran, R., Anderson, T., Agarwala, S., Venkatasubramanian, R., Gill, M., Gopalakrishnan, D., Hill, A., Chachad, A., Balasubramanian, D., Bhoria, N., Tran, J., Bui, D., Rahman, M., Moharil, S., Pierson, M., Mullinnix, S., Ong, H., Thompson, D., Gurram, K., Olorode, O., Mahmood, N., Flores, J., Rajagopal, A., Narnur, S., Wu, D., Hales, A., Peavy, K., Sussman, R.

“…The next-generation C66x DSP integrated fixed and floating-point DSP implemented in TSMC 40nm process is presented in this paper. The DSP core runs at 1.25GHz…”
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A 600 MHz VLIW DSP by Agarwala, S., Koeppen, P., Anderson, T., Hill, A., Ales, M., Damodaran, R., Nardini, L., Wiley, P., Mullinnix, S., Leach, J., Lell, A., Gill, M., Golston, J., Hoyle, D., Rajagopal, A., Chachad, A., Agarwala, M., Castille, R., Common, N., Apostol, J., Mahmood, H., Krishnan, M., Duc Bui, Quang-Dieu An, Groves, P., Nguyen, L., Nagaraj, N.S., Simar, R.

“…A 600 MHz VLIW DSP, which implements the C64x VelociTI.2/spl trade/ architecture delivers 4800 MIPS, 2400 (16 b) or 4800 (8 b) million multiply accumulates at…”
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A 800 MHz system-on-chip for wireless infrastructure applications by Agarwala, S., Wiley, P., Rajagopal, A., Hill, A., Damodaran, R., Nardini, L., Anderson, T., Mullinnix, S., Flores, J., Heping Yue, Chachad, A., Apostol, J., Castille, K., Narasimha, U., Wolf, T., Nagaraj, N.S., Krishnan, M., Nguyen, L., Kroeger, T., Gill, M., Groves, P., Webster, B., Graber, J., Karlovich, C.

“…The 800MHz System-on-Chip implements the C64x VLIW DSP VelociTI.2/spl trade/ Architecture and delivers 6400 MIPS, 3200 16-bit MMACs, 6400 8-bit MMACs at 0.17…”
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A 600MHz VLIW DSP by Agarwala, S., Koeppen, P., Anderson, T., Hill, A., Ales, M., Damodaran, R., Nardini, L., Wiley, P., Mullinnix, S., Leach, J., Lell, A., Gill, M., Golston, J., Hoyle, D., Rajagopal, A., Chachad, A., Agarwala, M., Castille, R., Common, N., Apostol, J., Mahmood, H., Krishnan, M., Duc Bui, Quang-Dieu An, Groves, P., Luong Nguyen, Nagaraj, N.S., Simar, R.

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